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VHDL in 1h
Martin Schberl
8/10/2019 VHDL in an hour
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AK: JVMHW VHDL 2
VHDL /= C, Java,
Think in hardwareAll constructs run concurrent
Different from software programming Forget the simulation explanation
VHDL is complex We use only a small subset
8/10/2019 VHDL in an hour
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AK: JVMHW VHDL 3
Signals are Wires
Use std_logic
std_logic_vector (n downto 0)
unsigned
Variables
Elegant for some constructs Easy to produce too much logic
Avoid them
8/10/2019 VHDL in an hour
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AK: JVMHW VHDL 4
Synchronous Design
Register Clock, reset
Combinatorial logicAnd, or,
+, -
=, /=, >,
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AK: JVMHW VHDL 5
Register
Changes the value on the clock edge
process(clk)
begin
if rising_edge(clk) then
reg
8/10/2019 VHDL in an hour
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AK: JVMHW VHDL 6
Register with Reset
Usually has an asynchronous reset
process(clk, reset)
begin
if (reset='1') then
reg
8/10/2019 VHDL in an hour
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AK: JVMHW VHDL 7
Combinational Logic
Simple expressions as signalassignment
Concurrent statement
a
8/10/2019 VHDL in an hour
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AK: JVMHW VHDL 8
Combinational Logic Complex expressions in a
process Sequential statement Input signals in the sensitivity
list Assign a value to the output for
each case
process(a, b)
begin
if a=b thenequal
8/10/2019 VHDL in an hour
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AK: JVMHW VHDL 9
Defaults for Combinationalprocess(a, b)
begin
equal
8/10/2019 VHDL in an hour
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AK: JVMHW VHDL 10
Constants
Single bit 0 and 1 Use for std_logic
Bit arrays 0011 Use for std_logic_vector andunsigned
Integer: 1, 2, 3 Use for integer, unsigned
8/10/2019 VHDL in an hour
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8/10/2019 VHDL in an hour
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AK: JVMHW VHDL 12
Counter in a Single Process-- we now use unsigned for the counter
signal reg : unsigned(7 downto 0);
begin
-- a single process:process(clk, reset) begin
if reset='1' thenreg '0');
elsif rising_edge(clk) thenreg
8/10/2019 VHDL in an hour
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AK: JVMHW VHDL 13
Quiz 1process(a, b, sel) begin
if sel='0' then
data
8/10/2019 VHDL in an hour
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AK: JVMHW VHDL 14
Quiz 2process(sel, a, b, c, d) begin
case sel iswhen "00" =>
data
data
data
data
8/10/2019 VHDL in an hour
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AK: JVMHW VHDL 15
Quiz 3process(sel) begin
case sel iswhen "00" =>
z
z z z z
8/10/2019 VHDL in an hour
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AK: JVMHW VHDL 16
Quiz 4process(clk, reset) begin
if reset='1' then
reg '0');
elsif rising_edge(clk) then
if en='1' thenreg
8/10/2019 VHDL in an hour
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AK: JVMHW VHDL 17
Quiz 5process(data, en) begin
if en='1' then
reg
8/10/2019 VHDL in an hour
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AK: JVMHW VHDL 18
User defined types
State machine states Operation type
type rgb_type is (red, green, blue);
signal color : rgb_type;
begin
color
8/10/2019 VHDL in an hour
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AK: JVMHW VHDL 19
A simple ALUtype op_type is (op_add, op_sub, op_or, op_and);signal op : op_type;
begin
process(op, a, b) begin
case op iswhen op_add =>
result
result
result
result
8/10/2019 VHDL in an hour
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AK: JVMHW VHDL 20
File structurelibrary ieee;use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu isport (
clk, reset : in std_logic;a_in, b_in : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0));end alu;
architecture rtl of alu issignal a, b : unsigned(7 downto 0);...
begina
8/10/2019 VHDL in an hour
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AK: JVMHW VHDL 21
Adder as Componentlibrary ieee;use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity add isport (
a, b : in std_logic_vector(7 downto 0);dout : out std_logic_vector(7 downto 0)
);end add;
architecture rtl of add is
signal result : unsigned(7 downto 0);signal au, bu : unsigned(7 downto 0);
beginau
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AK: JVMHW VHDL 22
Component Use Declaration
component add is
port (
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);dout : out std_logic_vector(7 downto 0)
);
end component add;
Instantiation
cmp_add: add port map (a_in, b_in, sum);
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AK: JVMHW VHDL 23
Componentlibrary ieee;
entity alu is
end alu;
architecture rtl of alu is
component add isport (a, b : in std_logic_vector(7 downto 0);dout : out std_logic_vector(7 downto 0)
);end component add;
signal a, b : unsigned(7 downto 0);signal sum : std_logic_vector(7 downto 0);
begina
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AK: JVMHW VHDL 24
State Machinearchitecture rtl of sm1 is
type state_type is (green, orange, red);signal state_reg : state_type;signal next_state : state_type;
begin
-- state registerprocess(clk, reset)begin
if reset='1' thenstate_reg
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8/10/2019 VHDL in an hour
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AK: JVMHW VHDL 26
State Machine in one Processarchitecture rtl of sm3 is
type state_type is (green, orange,red);signal state : state_type;
begin
-- single processprocess(clk, reset)
begin
if reset='1' thenstate
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AK: JVMHW VHDL 27
Summary
Think in hardware! Beware of unassigned pathes (latch!)
Use simple types Use simple statements
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AK: JVMHW VHDL 28
More Information
FAQ comp.lang.vhdl Mark Zwolinski, Digital System Design
with VHDL.
http://www.vhdl.org/comp.lang.vhdl/FAQ1.htmlhttp://www.vhdl.org/comp.lang.vhdl/FAQ1.html