Powering Your Ideas.TM
Austin DV Club
September 19, 2006
Zilker Labs Mixed-Signal VerificationZilker Labs Mixed-Signal Verification
2
Zilker Labs OverviewZilker Labs Overview
Mixed-signal Fabless Semiconductor VendorFounded in 2002Headquartered in Austin, TXTop-tier investors– Sevin Rosen– North Bridge– HIG
Experienced management team– Average of over 20 years experience
Corporate Strategy: Lead the transition to digital power conversion and control– 20+ fundamental architectural patents being filed– First IC, ZL2005, introduced October 3, 2005– Second IC, ZL2105, introduced July 31, 2006
3
Why Austin?Why Austin?
Mixed-signal design talentLocal venture capitalInfrastructure– Assembly– Failure analysis– Contract engineering available
4
Today’s Power IssuesToday’s Power Issues
Dense boards with thermal and board space challengesLow voltages, high currentsComplex power management requirements– Sequencing/tracking– Voltage margining– System monitoring– Fault detection and response– Etc…
5
Zilker Labs Digital-DCTM TechnologyZilker Labs Digital-DCTM Technology
Power management integrated with conversionMixed-signal implementation in digital CMOSEasy-to-use: no programming requiredIndustry leading efficiencyFlexible design environmentWide operating range
6
Complete System Power SolutionsComplete System Power Solutions
1A to 3A
3A to 6A
>30A
6A to 30A
Inte
rmed
iate
Bus
ZL2005
3SMBus
Thermal control
ZL2005
ZL2105
Multiphase
Wide portfolio of digital power conversion/management ICsEasy-to-implement management functionsSystem compatibility simplifies design processEasy to use development tools – PowerPilot™, Demo Board, App Notes
7
Smaller FootprintSmaller Footprint
1.0”1.0”
Using same footprintZL solution has:• Higher current• More features• Fewer components
0.6”
0.6”
0.4”
Optimizing 10A solutionfor very small sizeZL solution offers:
• Rich feature set• Fewer components• 60% smaller area
Analog ZL2005
Zilker
YesSMBus™PMBus™
No
YesPower ManagementNo
15Components4012.5 AIOUT max10 A14.0VVIN max13.2V4.5VVIN min10.8V
ZL2005Analog
8
Zilker Labs Design TeamZilker Labs Design Team
Analog 30%Digital 40%Firmware 20%DSP algorithm Development 10%
9
Verification ChallengeVerification Challenge
Analog block functionalityDigital functionalityAnalog-Digital interfaceFirmware actually defines productHow do you know you are done?
10
System ArchitectureSystem Architecture
DAC
Transient Detector
DIGITALPID FILTER
Intermediate Bus Voltage
VOUTM
OS
FET
Drivers
BST
LDO
SW
VSNS
Digital Ref
D-PWM
MLC
+Σ
-
Conversion
Legend
TRIM/VSET
RESET
Sync
I2C,PMBus
ADC
PLL
Power Management Logic
ManagementVREF
MUX
VDD
Temp
TEMPI-LIMIT
Start DelayMarginEnable
VoltagesetPgood
Address/Phase Select
RampRate
MO
SFE
TD
rivers
BST
LDO
SW
VSNS
Digital Ref
D-PWM
High Voltage
11
Analog BlocksAnalog Blocks
SpecificationsDesign ReviewsVerilogAMS models“Fast” spice system simulations
12
DigitalDigital
Two parts– DSP functionality– Control functionality
Directed testsVerified as a platformEmulation– DSP function in real time– Enables algorithm verification– Simulation is TOO SLOW
13
Emulation PlatformEmulation Platform
14
Verilog AMSVerilog AMS
Aaron Shreeve will now present how we used the VerilogAMS flow
15
Thank YouThank You
www.zilkerlabs.com
Powering Your Ideas.Powering Your Ideas.TMTM