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2011 International Conference on Electronics and Optoelectronics (ICEOE 2011)

Probabilistic Arithmetic for JPEG Image Processing Application

Xiaoming Yang1,a, Yonghong Li1,b, Yujian Jin1,", Fengying Yue1,d, Enhuai Wang1, Zhiyong xu1

l. College of Information and Communication Engineering in North University of China, Taiyuan, Shanxi 030051 a. [email protected]; b. [email protected]; c. [email protected]; d. [email protected];

Abstract-The purpose of my project is to investigate the use of probabilistic hardware (arithmetic approach in my project) in multimedia processing applications. To complete the project, first, I use full adders to constitute the ripple carry adders. Then these devices are used in jpeg encoding program and recording the results of peak signal-to-noise ratio (PSNR) and power consumption under different conditions. According to the probabilistic characteristics of the devices, I modified the algorithm of the ripple carry adders and multipliers, which will raise the peak signal-to-noise ratio and decrease power consumption efficiently. At last, I compare the results of deterministic encoding and probabilistic encoding and the modified probabilistic encoding results on image processing and get the conclusions.

Keywords-Probabilistic encoding, full adders, PSNR.

I. INTRODUCTION

Image and video data compression refers to a process in which the amount of data used to represent image and video is reduced to meet a bit rate requirement (below or at most equal to the maximum available bit rate), while the quality of the reconstructed image or video satisfies a requirement for a certain application and the complexity of computation involved is affordable for the application. In this dissertation, we focus on the peak signal noise ratio and power consumption of colorful images encoding to investigate the behavior of the nano-scale semiconductor devices.

Nano-scale electronic circuits would unavoidably show probabilistic behavior. And the effect of encoding jpeg image with probabilistic hardware has not been investigated before. To evaluate the effect or performance of the encoding, I focus on the accurate of pictures and energy cost in encoding with the parameters peak signal noise ratio and power consumption of a single full adder. By simulating the probabilistic behavior and encoding and getting results of them, I can compare the performance between probabilistic hardware and deterministic hardware and then modified the algorithm to increase the accuracy and decrease the energy consumption.

II. SIMULATION OF A FULL ADDER WITHPSPICE

A. The probabilistic behavior and power consumption of a full adder

To implement probabilistic Boolean logic, a probabilistic gate produces a desired value as an output that is 0 or 1 with probability p, and, hence, can produce the wrong output value with a probability (1 - p) [1] [2]. Figure I shows the typical probabilistic full adder model.

A B

C Cin

Noise_ I

Sum

. .., QJ

.!!! o z

Figure I. A Full Adder

Figure 1 shows how a noise source can be added to the output of a full adder (FA) circuit to make a probabilistic full adder (PF A) circuit. In Figure I, a "P" denotes a probabilistic output, and the noise sources Noise and Noise are independent of each other.

TABLE 1. RELATIONSHIP BETWEEN VOLTAGE AND PROBABILITY OF ERROR OCCURS

Vo1tage( Pro b ability of error 0 C cur�J � V)�J

0.8 �J 0.0231 �J � 0.9 �J 0 0127 �J �

1.0 �J 0.0065�J �

1.1 �J 0.0028�J � 1.2 �J 0.00 1 3�J �

1.3 �J O�J �

The voltage of a full adder affects the probability of error occurs. The higher voltage the lower probability of error occurs. In my work, the relationship between voltage and probability of error occurs is shown in TABLE I.

B. The structure of a ripple carry adder A6 B6 A5 B5 A4 B4 A3 B3

A2 B2 A I B I AO BO

\�------,-----�I I

Detenninistic Full Adders

\ /

Probabilistic FL Adders

Figure 2. Typical Probabilistic Ripple Carry Adder

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Figure 2 is a typical probabilistic ripple carry adder. In practice, as shown in Figure 2, the adders which cal��la�e the several more significant bits are set to be determmlstlc while adders which calculate the several less significant bits are set probabilistic. So the probabilistic error numbers and corresponding voltage of the full adder determine the character of the ripple carry adder. This rule is also suitable for multipliers.

III. PROBABILISTIC JPEG ENCODING

Basically, an encoder is made up by multipliers and ripple carry adders which are used to real

.iz� multiplic�tion

and addition correspondingly. Both multiplIers and rIpple carry adders can be designed to consist of full adders. Fig�re 3 shows the relationship between full adders and encodmg processing. In OCT part, ripple carry adders and multiplies are used and in quantization part, only multipliers are used.

adder-

Figure 3. Devices used in JPEG Encoding

I did the simulation of the jpeg encoding program in C programming language. In quantization part, there are 64 coefficients of quantization. To investigate the characters of these coefficients under probabilistic encoding, the 64 coefficients are divided into three parts according to their original order. There are four factors which affect the PSNR and the power consumption as follows:

1, OCT error bits of RCA: the probable number of Error

bits in ripple carry adders;

2, OCT error voltage of RCA; the voltage of the

probabilistic bits in ripple carry adders;

3, OCT error bits of multiplier; the number of error bits

in multiplier of OCT part;

4, OCT error voltage of multiplier: the voltage of the

probabilistic bits in multiplier of OCT part; .

We will see the contrast images with two groups m different parameters. The parameter of each encoding picture is shown with the same order.

. . . . In DCT part, ripple carry adder's probabIlIstIc behavIOr

PSNR and power under different error bits, the parameters are selected as follows in an order described before. Ripple carry adder's probabilistic behavior PSNR and power under different error bits, the parameters are selected as follows: the OCT error bits of RCA, the first group is 2, the second is 8. Figure 4 shows that picture encoded by 2 error bits ripple carry adder has a better PSNR than 8 bits error bits one while the former consume more power.

Figure 4. Ripple Carry Adder's Probabilistic Behavior PSNR and Power under Ditlerent Error Bits

PSNR and power under different error voltage, the parameters are selected as follows: the OCT error voltage of RCA, the one is 1.2, and the other is 0.8. Figure 5 shows that if the voltage of the error bits of ripple carry adder is higher, the PSNR is better while the former consume more

Figure 5. PSNR and Power under Ditlerent Error Voltage

PSNR and power under different error bits, the parameters are selected as follows: the DCT error bits of multiplier, the first is 11, and the second is 16. Figure 6 show that picture encoded by fewer error bits multiplier in OCT has a better PSNR than more error bits one while the former

Figure 6. PSNR and Power under Ditlerent Error Bits

PSNR and power under different error voltage, the parameters are selected as follows: the OCT error voltage �f multiplier, first is 1.2, second is 0.8. Figure 7 shows that If the voltage of the error bits of multiplier in DCT is higher, the PSNR is better while the former consume more power.

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Figure 7. PSNR and Power under Ditlerent Error Voltage

Different coefficients assign, the parameters are selected as follows, the Quantization part I coefficient number: one is 61, two is 21; the Quantization part I error voltage: one is 1.2, two is 1.2; the Quantization part 2 coefficient number: one is 2, two is 22; the Quantization part 2 error voltage: one is 1.0, two is 1.0; the Quantization part 3 error voltage: one is 0.8, two is 0.8. Figure 8 shows that if more coefficients are encoded by multiplier which has fewer probable error bits and higher voltage the corresponding picture have better PSNR and more

.

Figure 8. PSNR and Power under Different Coefficient Assign

IV. MODIFICA nON IN PERFORMANCE OF ENCODING

The DCT part is computation intensive and we can optimize the DCT part by dividing it into two procedures and using corresponding probabilistic devices.

&-0

Figure 9. Data Flow of 8 Points 1-0 OCT

Figure 9 shows the whole data flow of the 8 points dimensional DCT algorithm used in my simulation. For the realization of this modified DCT, we can find that before multiplication we only need 16 bits length ripple carry adder, while after the multiplication, 32 bits ripple carry adders are needed. So if we use these two kinds of ripple carry adders and realize the encoding, accuracy can be improved and the power consumption can also be cut down at the same time. But this method will increase the complexity of the chip design.

(a) (b) Figure 10. Using the New Ripple Carry Adder Model in Ditlerent Energy

Consumption and PSNR

Figure 10 is the comparison chart. Picture(a) is example of approximate 96.5% energy consumption of all deterministic RCA,PSNR is 40.2. Picture (b) is example of approximate 81.5% energy consumption of all deterministic RCA, PSNR 14.8. From Figure 10 (a) and (b) we can see that using the new ripple carry adder model, the fewer probabilistic error bits, the better PSNR and more power consumption will been obtained by the encoding processing.

V. CONCLUSION

It is believed that probabilistic computing has potential for multimedia applications[3][4]lII i'i! I * it �J 01 III �.

• In fact, multimedia applications often have margin for errors because the human brain can naturally compensate for less-than-perfect multimedia content. It is hoped that by observing images generated by the C-based JPEG encoder with possibly incorrect DCT computation, we are able to have a rough impression of whether probabilistic RCA can be used in a realistic embedded JPEG encoder.

In this thesis we use a model of characterization of probabilistic gates (full adder model and the probabilistic table model). An application example is shown where a probabilistic ripple carry adder is simulated in a software-based JPEG encoder. [t shows that some amount of errors can be tolerated while maintaining acceptable visual quality (e.g., PSNR). This may provide a clue about how to realize error-resilient hardware for JPEG encoder in future noisy CMOS technologies.

Whereas, truncating the LSBs of an adder would incur much error which can not be tolerated by the encoder without sacrificing the quality of the compressed images. This suggests that, instead of using a "hard" approach of truncating the LSBs for saving resources, e.g., by turning of the hardware or putting to "sleep", one may consider a "soft" approach, namely, to save resources by trading off a slight

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degree of computation accuracy. This is the main idea of probabilistic computing.

REFERENCE

[I] A. Bhanu. M. S. K. Lau, K. V. Ling, V. l Mooneylll, and A. Singh, "A more precise model of noise based CMOS errors," Proceedings of DELTA, 2010, pp. 99-102.

[2] M. S K. Lau, K. V. Ling, Y C Chu, and A. Bhanu,"Modeling of probabilistic ripple-carry adders," Proceedings of DELTA, 2010, pp. 201-206.

[3] 1. M. Rabaey, A. Chandrakasan, and B. Nikoli' c, Digital Integrated Circuits: A Design Perspective, 3rd ed. Prentice Hall, 2003.

[4] M. S K. Lau, K. V. Ling, Y C Chu, and A. Bhanu, "Modeling of probabilistic ripple-carry adders," in Proceedings of the 5th IEEE International Symposium on Electronic Design, Test & Applications (DELTA), January 2010.

[5] P. Korkmaz, B. E. S Akgul, and K. V. Palem, "Energy, performance, and probabil ity tradeoffs for energy-efficient probabil istic CMOS circuits," IEEE Transactions on Circuits and Systems I, vol. 55, no. 8, pp. 2249-2262, September 2008.

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