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May 4, 2011
Integrated Power Management
Silicon Platforms for Fabless
Design in the 5V- 700V Range
May 4, 2011
Dr Shye Shapira
Director of RD Integrated Power Management Platforms
TowerJazz
May 4, 2011
Integrated Power Management Applications are Thriving
Portable devices are proliferating: Including multiple subsystems with different voltage ratings that require multiple power management circuits.
Green (Efficient) Offline Applications: Small size conversion circuitry from Grid to a low voltage application power. Highest volume application: home LED lights.
May 4, 2011
From IDM Monopoly to Foundry –Fabless Relation
Last three years and ongoing: Process Design kits available from Foundries 60V, 200V, 700V
Until then : Integrated Power Management Design almost all Independent Device Manufacturer
May 4, 2011
Impact on the Israeli Fabless Arena
Growing Market +Foundry Availability of Power Management
Platforms +Large Fabless Community +2 to 5 years =
Most Fabless companies in Israel ( as in most other places…) design integrated PM Chips
May 4, 2011
The Odds For/Against Fabless Power Design
Independent Power Device Manufacturer
Time
Europe/US 2011(Tradition in PMIC* design)
Israel 2011(No tradition in PMIC* design
but analog /digital design community)
Engineering Work Force Migration
*PMIC=Power Management Integrated Circuits
Production Worthy PMIC Design Capability
Production Worthy PMIC Design Capability
Digital Intensive
IDM
UniversitiesAnalog /RF
Design Houses
Fabless Start Up
Engineering Work Force Migration
Learning Cycles
Production Worthy PMIC Design Capability
Fabless Start Up
Power Supply Makers
May 4, 2011
Evening Out the OddsU.S. Wild West 1860 s:
”God created man,
but Samuel Colt made them Equal.“
Integrated Power Management Design 2011 :
” Advanced Foundry Power Management Design Platforms, Process Design Kits and Design Service make Design Capabilities Equal.“
May 4, 2011
Challenges in Power Management Platform Design
Quality How it is achieved Through what means
Efficiency Switching speed: QgRon Specific
Device /Platform Design
Small Area Low Ron SpecificSmall Footprint Esd Solution
Dense Logic
Device /Platform Design
Integration Logic+Analog PlatformNVM
Isolation: Buried LayerDevice /Platform
Design
Automation/Circuit Robustness
ModelingDRC
LayoutRules for Multiple Voltage
Nodes
Advanced KitDesign Support Layout Practices
May 4, 2011
Integrated Power Management Application Space
5v-60V
• DC DC Converter (“Boost Buck” Convertors Std Alone, Digital Cameras)
• LED Drivers
• Motor Drives
• Line Drivers
• Class D Audio Amplifiers. Low Ron and low noise.
• Power over Ethernet
• RF Power Amplifiers
150v-700V
• Offline applications AC adapter
– Voltages 400 to 600V
– Lighting
May 4, 2011TowerJazz Confidential
5-60V : PMIC and the Self Aligned Body Ldmos
DrainChannelSelf aligned Body option Allows short channel ,Low specific RdsonIsolated Source
Channel
Two Process options to allow reduced RdsonScalable drain allows proper voltage BV relation
May 4, 2011
Transistor is mad of a 2D array of
fingers. #Nf=Nr*Nc
Calculators: operating
voltage, Breakdown voltage, Ron
with or without the M2 routing
Drift region or operating voltage
choosing box/switch
Thermal resistance flag
Routing options
Guard Ring options: no G.R, PM
rings (up to 5) or P+AA ring
Advanced options, will be
allowed at future PDK
Scalable Voltage :
Best Device Area tradeoff for
required voltage
Guard Ring Selection in Pcells
Parasitic Metal Resistance Calculator
Pcell Features & GUI of a scalable voltage LDMOS
May 4, 2011
Isolation Challenge In Integrated Power Management Circuits
AnalogBgref
(I~microA)
Deep Nwell
HV Pwell (PHV)
PolyP+
M1
Emitter
M1
Base
PolyP+ N+
M1
Base
N+ N+
M1
Collector
M1
Collector
HV VNPN Biploar
1. Current (Several Amps) Drawn From Substrate by inductor through ldmos
drain affects all other low current (microA-mA) circuitry via noise or
latchup risk.
2. Minority Carriers injected by diode may still diffuse to substrate through
isolating layer
May 4, 2011
5V-60V Isolated Platforms
TowerJazz Confidential
Shallow NBL Deep NBL
Shallow NBL: Buried layer shorted to drain Deep NBL: Buried layer Isolated
Allows drain Isolation
May 4, 2011
700V platform
• Logic
• Density
• Analog
• Rdson: Resurf
May 4, 2011
700V NLDMOS
Double Resurf: Isolation layerPinched off on both sides
Layout Examples:
700v LdmosDevice and
Building Blocks
May 4, 2011
Zener Diode in 700V Process
•BV = 6V
•Can Float to 50V
•No Walk out
May 4, 2011
Additional Material
• Chipex 2010: Integrated Power Management Platforms: Applications Production and Figures of Merit.
• ASCR Technion: Integrated Power Management Circuit Platforms: Figures of Merit, Features and their correlation to applications.
• GSA Forum: Integrated Power Management Platforms: The Entry of Fabless Design Houses to Power Management System Design
