Designing State Machine

Designing State Machines Using State Diagrams

• Design a state machine to control the tail lights of a 1965 Ford Thunderbird. The tail lights are composed of three light on each side which operate for the turns in the manner shown in the picture next.


• The state machine has:– Three inputs: left, and right turns,

and hazard.

– Six outputs: LA, LB, LC, RA, RB, and RC.

– Free running clock with frequency equal to the flashing rate.


• LA = L1+L2+L3+LR3• LB = L2+L3+LR3• LC = L3+LR3• RA = R1+R2+R3+LR3• RB = R2+R3+LR3• RC = R3+LR3

• State name represents a logic expression that is 1 only in that state

• The output equations may be written without assigning coded states

For the state diagram to be unambiguous: The transition expressions on the arcs leaving each state have to be mutually exclusive and all inclusive. That is, for each state, no two expressions are 1 for the same input combination, and some expression is 1 for every input combination.

This can be confirmed algebraically by performing two steps

Mutual exclusion: For each state, show that the logical product of each pair of transition expression on arcs leaving that state is zero. If there are n arcs, then there are n(n-1)/2 logical products to evaluate.

All inclusion: For each state show that the logical sum of the transition expressions on all arcs leaving the state is 1.

The state diagram in not mutually exclusive

because for some input combinations more than one transition expressions are 1.

I/p combinations

Transition Expressions

Le Ri Ha L R H

0 0 0 0 0 0 1

0 0 1 0 0 1 0

0 1 0 0 1 0 0

0 1 1 0 1 1 0

1 0 0 1 0 0 0

1 0 1 1 0 1 0

1 1 0 1 1 0 0

1 1 1 1 1 1 0

HRL

State IDLE

• Some of the logical products for each pair of transition expression on arcs leaving IDLE state is not zero.For the state IDLE

Arcs leaving the state: 4

L, R, H,

Logical products to evaluate:4*3/2 = 6

L·R ≠ 0, L·H ≠ 0, R·H ≠ 0

L· = 0

R· = 0

H· = 0• All inclusion: For each state the logical

sum of the transition expressions on all arcs leaving the state is one.

L+R+H+

HRL

HRL HRL

HRL

1 HRL

Problem- The state diagram doesn’t handle

multiple inputs asserted simultaneously. That is, what happens in the IDLE state if both LEFT and HAZ are asserted? According to the state diagram the machine goes into two states L1 and LR3 which is impossible.

The problem is avoided by giving HAZ input a priority. Also we treat both LEFT and RIGHT asserted simultaneously as a Hazard request, since the driver is completely confused and requires help.

The state diagram in now mutually exclusive

I/p comb-inations

Transition Expressions

Le Ri Ha

0 0 0 0 0 0 1

0 0 1 0 1 0 0

0 1 0 0 0 1 0

0 1 1 0 1 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 1 0 0

1 1 1 0 1 0 0

HRL

State IDLE

HRL

RHL

LHR

• The logical products for each pair of transition expression on arcs leaving IDLE state is zero.

For the state IDLE

Arcs leaving the state: 4

Logical products to evaluate:4*3/2 = 6

All 6 products are zero.

• For each state the logical sum of the transition expressions on all arcs leaving the state is one.

• Hence the state diagram now is both mutually exclusive and all inclusive

HRL ,HRL ,LHR ,RHL

• In the new state diagram we notice that once the turn has been initiated the state diagram allows the cycle to run to completion even if HAZ is asserted.

This may have a certain aesthetic appeal, however it would be safer to allow the machine to go into Hazard mode as soon as possible.

• Hence the state diagram is modified as shown next.

State Assignment• IDLE state of 000.

• Q1 and Q0 are used to count in gray code sequence (IDLE→L1→L2→L3→IDLE) (IDLE→R1→R2→R3→IDLE).

• Q2 identifies LEFT or RIGHT turn.

• HAZ state of 100.

Transition List

• Next step – sort of transition table• In this case the transitions are specified

by expressions rather than an exhaustive tabulation of next states

Synthesis using transition List

• Develop a set of transition equations that define the next state variable S* in terms of current state S and inputs

• The transition list may be viewed as a sort of hybrid truth table in which the state-variable combinations for the current state are listed explicitly and input combinations are listed algebraically.

• Reading down a S* column find a sequence of 0s and 1s indicating the value of S* for various state/input combinations.

• A transition equation for a next state variable S* can be written using a sort of hybrid canonical sum.

• S* = ∑ (transition p-term)

Transition list rows where S* = 1


• Transition p-term is the product of the current states min-term and the transition expression.

• The transition equation has one transition p-term for each row of the transition list that contains a ‘1’ in the S* column.

• There is no guarantee that the transition equations obtained by this method are in any sense minimal.

• The equations are not even in the standard POS or SOP forms

• They only provide a starting point for whatever combinational design method one might choose to synthesize the excitation logic for the FSM


• Based on the transition list we get the following transition equations for Q2*, Q1* and Q0*

HRLQQQQ 012*2

HRLQQQ 012

HQQQ 012 HQQQ 012

HQQQ 012 HQQQ 012

HQQQ 012 HQQQ 012

HRQQQQ 012*2

HQQ 02 02 QQ


HRLQQQQ 012*0

HRLQQQ 012

HQQQ 012 HQQQ 012

HQQQHQQQQ 012012*1

HQQQHQQQ 012012

HQQ 0*1

RLHQQQQ 012*0

HQQ 01

Excitation equations

• On deriving the transition equations it is desirable to use the D flip flops as memory elements

• The transition equation directly gives the excitation equation in this case

• The excitation equations of other flip-flops are not so easy to derive

• Majority of the PLD & ASIC based systems employ D flip flops.

Variations in the scheme

• If the column for a particular next state variable contains fewer 0s than 1s, it may be advantageous to write that variables transition equation in terms of 0s in its column

)(*0*

Swhererowslisttransition

termsptransitionS

• That is for all the p terms for which

• Thus a transition equation may be written for as the sum of 7 p-terms

1* S0* S

*2Q

HRLQQQQ 012*2

HRLQQQ 012

HQQQ 012 HQQQ 012

1012 QQQ 1012 QQQ

1012 QQQ

Variations in the scheme

• To obtain an expression for we simply complement both sides of the reduced equation

• To obtain an expression for a next state variable directly, using the 0s in the transition list, we can complement the right hand side of the general equation using DeMorgan’s theorem, obtaining a sort of hybrid canonical product

0*

)(*Vwhererowslisttransition

termsstransitionV

RHQQQQ 012*2 HQQ 02

01 QQ 02 QQ

*2Q

*V

*V

•Transition s-term is the sum of the current states max-term and the complement of the transition expression.

Unused states

• In this problem there were no unused states

• However, in case there are some unused states in the problem then they do not reflect in the transition list

• They are treated as don’t care in a very limited sense

• While writing equations for S*, the sum of p-terms for rows that had an explicit 1 in the corresponding column were taken

• Although we don’t consider the unused states, the procedure implicitly treats them as if they had 0s in the corresponding column

• Conversely for the procedure implicitly treats unused states as if they had 1s in the corresponding column

*S

Output-Coded state assignment• The machines outputs are a function of

state only• A different output combination is

produced in each named state• We can use the outputs as state variables

and assign each named state to the required output combination

• This sort of assignment is termed as output-coded state assignment

• Sometimes results in excitation equations that are simpler than the set of excitation and output equations obtained with a state assignment using minimum number of state variables

• It saves cost in a PLD based design since fewer PLD macrocells or outputs are needed overall

• Current State| Transition Exp| Next State

Decomposing State Machines

• Just like large programs being decomposed into procedures or subroutines, large state-machine problems are often solved with a collection of smaller state machines

• The original design problem is put into a natural hierarchical structure, so that the functions and uses of the sub-machines are obvious, making it unnecessary even to write a state table for the sub-machine

• The most commonly used sub-machine is a counter. The main machine usually STARTS the counter when it wishes to stay in a particular main state for n counts

• The counter counts the n counts and sends a DONE signal when the count is completed


• The main machine is designed to wait in the same state till it receives the DONE signal from the sub-machine

• This adds an extra output and input to the main machine (START and DONE) but saves n -1 states

• The simplest type of decomposition is shown in figure

• The Main machine provides the primary inputs and outputs and executes the top level control algorithm.

• The sub-machines perform the lower level functions under the control of the main machine and may also optionally handle some of the primary inputs and outputs

Main Machine

Sub Machine

1

Sub Machine

2

Start 1

Done 1

Start 2

Done 2

Inputs Outputs

Typical hierarchical state-machine structure


Education

Designing State Machine