Binary Logic and GatesBinary Logic and Gates Logic SimulationLogic Simulation Boolean AlgebraBoolean Algebra NAND/NOR and XOR gatesNAND/NOR and XOR gates Decoder fundamentalsDecoder fundamentals Half Adder, Full Adder, Ripple Carry AdderHalf Adder, Full Adder, Ripple Carry Adder

Digital Logic CircuitsDigital Logic Circuits

Analog vs DigitalAnalog vs Digital

AnalogAnalog– ContinuousContinuous

» Time Every time has a value associated with it, not just some times

» Magnitude A variable can take on any value within a range

» e.g. temperature, voltage, current, weight, length, brightness, color

Digital SystemsDigital SystemsDigital vs. Analog Waveforms

Analog: values vary over a broad range continuously

Digital: only assumes discrete values

+5

V

–5

T ime

+5

V

–5

1 0 1

T ime

QuantizationQuantization

Analog vs DigitalAnalog vs Digital

DigitalDigital– DiscontinuousDiscontinuous

» Time (discretized) The variable is only defined at certain times

» Magnitude (quantized) The variable can only take on values from a finite set

» e.g. Switch position, digital logic, Dow-Jones Industrial, lottery, batting-average

Analog to DigitalAnalog to Digital

A Continuous Signal is Sampled at Some Time and Converted to A Continuous Signal is Sampled at Some Time and Converted to a Quantized Representation of its Magnitude at that Timea Quantized Representation of its Magnitude at that Time– Samples are usually taken at regular intervals and controlled by a Samples are usually taken at regular intervals and controlled by a

clock signalclock signal

– The magnitude of the signal is stored as a sequence of binary valued The magnitude of the signal is stored as a sequence of binary valued (0,1) bits according to some encoding scheme(0,1) bits according to some encoding scheme

Digital to AnalogDigital to Analog

A Binary Valued, B = { 0, 1 }, Code Word can be Converted to its A Binary Valued, B = { 0, 1 }, Code Word can be Converted to its Analog ValueAnalog Value

Output of D/A Usually Passed Through Analog Low Pass Filter to Output of D/A Usually Passed Through Analog Low Pass Filter to Approximate a Continuous SignalApproximate a Continuous Signal

Many Applications Construct a Signal Digitally and then D/AMany Applications Construct a Signal Digitally and then D/A– e.g., RF Transmitters, Signal Generatorse.g., RF Transmitters, Signal Generators

Digital is UbiquitousDigital is Ubiquitous

Electronic Circuits based on Digital Principles are Widely UsedElectronic Circuits based on Digital Principles are Widely Used– Automotive Engine/Speed ControllersAutomotive Engine/Speed Controllers

– Microwave Oven ControllersMicrowave Oven Controllers

– Heating Duct ControlsHeating Duct Controls

– Digital WatchesDigital Watches

– Cellular PhonesCellular Phones

– Video GamesVideo Games

Why Digital?Why Digital?

Increased Noise ImmunityIncreased Noise Immunity ReliableReliable InexpensiveInexpensive ProgrammableProgrammable Easy to Compute Nonlinear FunctionsEasy to Compute Nonlinear Functions ReproducibleReproducible SmallSmall

Digital Design ProcessDigital Design Process

Computer Aided Design ToolsComputer Aided Design Tools– Design entryDesign entry

– SynthesisSynthesis

– Verification and simulationVerification and simulation

– Physical designPhysical design

– FabricationFabrication

– TestingTesting

DefinitionDefinition

Exclusive-or (Exclusive-or (XOR, EXORXOR, EXOR, , not-equivalence, ring-ORnot-equivalence, ring-OR)) Algebraic symbol:Algebraic symbol: Gate symbol:Gate symbol:

Representations for combinational logicRepresentations for combinational logic Truth tablesTruth tables Graphical (logic gates)Graphical (logic gates) Algebraic equations (Boolean)Algebraic equations (Boolean)

Boolean algebra & logic circuitsBoolean algebra & logic circuits

Representations of a Digital DesignRepresentations of a Digital Design

Truth Tables

tabulate all possible input combinations and their associated output values

Example: half adder adds two binary digits to form Sum and Carry

Example: full adder adds two binary digits and Carry in to form Sum and Carry Out

NOTE: 1 plus 1 is 0 with a carry of 1 in binary

A B

0 0 1 1

0 1 0 1

Sum Carry

0 1 1 0

0 0 0 1

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C in 0 1 0 1 0 1 0 1

S um 0 1 1 0 1 0 0 1

C out 0 0 0 1 0 1 1 1

Representations of Digital Design: Representations of Digital Design: Boolean AlgebraBoolean Algebra

NOT X is written as XX AND Y is written as X & Y, or sometimes X YX OR Y is written as X + Y

values: 0, 1variables: A, B, C, . . ., X, Y, Zoperations: NOT, AND, OR, . . .

A

0011

B

0101

Sum

0110

Carry

0001

Sum = A B + A B

Carry = A B

OR'd together product terms for each truth table

row where the function is 1

if input variable is 0, it appears in complemented form;

if 1, it appears uncomplemented

Deriving Boolean equations from truth tables:

Representations of a Digital Representations of a Digital Design: Boolean AlgebraDesign: Boolean Algebra

A

00001111

B

00110011

Cin

01010101

Sum

01101001

Cout

00010111

Another example:

Sum = A B Cin + A B Cin + A B Cin + A B Cin

Cout = A B Cin + A B Cin + A B Cin + A B Cin

Gate Representations of a Digital DesignGate Representations of a Digital Designmost widely used primitive building block in digital system design

StandardLogic Gate

RepresentationHalf Adder Schematic

Netlist: tabulation of gate inputs & outputs and the nets they are connected to

Net: electrically connected collection of wires

Inverter

AND

OR

Net 1

Net 2

A

B

CARR Y

SUM

Design methodologyDesign methodology

Top-down vs. bottom-up designTop-down vs. bottom-up design

Analysis proceduresAnalysis procedures

Schematic for 4 Bit ALUSchematic for 4 Bit ALU

ANDGate

ORGate

EXOR

Gate

Invertor

Simulation of 4 Bit ALUSimulation of 4 Bit ALUif if SS=0 then =0 then D=BD=BAAif if SS=1 then =1 then D=AD=ABBif if SS=2 then =2 then D=A+BD=A+Bif if SS=3 then =3 then D=D=AAS

B

AD

4

2

4

Elementary Binary Logic FunctionsElementary Binary Logic Functions Digital circuits represent information using two voltage levels.Digital circuits represent information using two voltage levels.

– binary variablesbinary variables are used to denote these values are used to denote these values

– by convention, the values are called “1” and “0” and we often think of by convention, the values are called “1” and “0” and we often think of them as meaning “True” and “False”them as meaning “True” and “False”

Functions of binary variables are called Functions of binary variables are called logic functionslogic functions..– AND(AND(AA,,BB) = 1 if ) = 1 if AA=1 and =1 and BB=1, else it is zero. =1, else it is zero.

» AND is generally written in the shorthand AB (or A&B or AB)

– OR(OR(AA,,BB) = 1 if ) = 1 if AA=1 or =1 or BB=1, else it is zero. =1, else it is zero. » OR is generally written in the shorthand form AB (or A|B or AB)

– NOT(NOT(AA) = 1 if ) = 1 if AA=0 else it is zero. =0 else it is zero. » NOT is generally written in the shorthand form (or A or AA

AND, OR and NOT can be used to express all other logic functions.AND, OR and NOT can be used to express all other logic functions.

Two Variable Binary Logic FunctionsTwo Variable Binary Logic Functions

Can make similar Can make similar truth tablestruth tables for 3 variable or 4 variable functions, for 3 variable or 4 variable functions, but gets big (256 & 65,536 columns).but gets big (256 & 65,536 columns).

ZER

O

0000

A0011

B0101

NO

R

1000

A

1100

0100

0010

B

1010

NA

ND

1110

EX

OR

0110

AN

D

0001

EQ

UA

L

1001

1101

B0101

A0011

1011

ON

E

1111

OR

0111

Representing functions in terms of AND, OR, NOT.Representing functions in terms of AND, OR, NOT.– NAND(NAND(AA,,BB) = ) = AABB))– EXOR(EXOR(AA,,BB) = () = (AABB) ) ( (AABB ))

Basic Logic GatesBasic Logic Gates

Logic gates “compute” elementary binary functions.Logic gates “compute” elementary binary functions.– output of an AND gate is “1” when both of its inputs are “1”, output of an AND gate is “1” when both of its inputs are “1”,

otherwise the output is zerootherwise the output is zero

– similarly for OR gate and invertersimilarly for OR gate and inverter Timing diagram shows how output values change over time as Timing diagram shows how output values change over time as

input values changeinput values change

XY XYAND Gate

X X’Inverter

XYXY

OR Gate

X’

XY

X+Y

X

Y

Timing Diagram

Multivariable GatesMultivariable Gates

AND function on AND function on nn variables is “1” if and only if ALL its variables is “1” if and only if ALL its arguments are “1”.arguments are “1”.– nn input AND gate output is “1” if all inputs are “1” input AND gate output is “1” if all inputs are “1”

OR function on OR function on nn variables is “1” if and only if at least one of its variables is “1” if and only if at least one of its arguments is “1”.arguments is “1”.– nn input OR gate output is “1” if any inputs are “1” input OR gate output is “1” if any inputs are “1”

Can construct “large” gates from 2 input gates.Can construct “large” gates from 2 input gates.– however, large gates can be less expensive than required number of 2 however, large gates can be less expensive than required number of 2

input gatesinput gates

ABC

3 input AND Gate

ABCDEF

6 input OR Gate

ABC

A

CB

D

FE

Elements of Boolean AlgebraElements of Boolean Algebra Boolean algebra defines rules for manipulating symbolic binary logic Boolean algebra defines rules for manipulating symbolic binary logic

expressions.expressions.– a symbolic binary logic expression consists of binary variables and the a symbolic binary logic expression consists of binary variables and the

operators AND, OR and NOT (e.g. operators AND, OR and NOT (e.g. AA++BBCC)) The possible values for any Boolean expression can be tabulated in a The possible values for any Boolean expression can be tabulated in a

truth tabletruth table..A B C BC A+BC00001111

00110011

01010101

00100010

00101111

ABC

A+BC

Can define circuit forCan define circuit forexpression by combiningexpression by combininggates.gates.

Schematic Capture & Logic SimulationSchematic Capture & Logic Simulation

gates

terminals

wires

schematicentry tools

signalwaveforms

signalnames

advancesimulation

Boolean Functions to Logic CircuitsBoolean Functions to Logic Circuits Any Boolean expression can be converted to a logic circuit made up of Any Boolean expression can be converted to a logic circuit made up of

AND, OR and NOT gates.AND, OR and NOT gates.

step 1: step 1: add parentheses to expression to fully define order of add parentheses to expression to fully define order of operations - operations - AA+(+(BBCC ))))

step 2:step 2: create gate for “last” operation in expressioncreate gate for “last” operation in expression

gate’s output is value of expressiongate’s output is value of expression

gate’s inputs are expressions combined by operationgate’s inputs are expressions combined by operation

AA+BC

(BC))step 3:step 3: repeat for sub-expressions and continue until donerepeat for sub-expressions and continue until done

Number of Number of simplesimple gates needed to implement expression equals gates needed to implement expression equals number of operations in expression.number of operations in expression.– so, simpler so, simpler equivalent expressionequivalent expression yields less expensive circuit yields less expensive circuit

– Boolean algebra provides rules for simplifying expressionsBoolean algebra provides rules for simplifying expressions

Basic Identities of Boolean AlgebraBasic Identities of Boolean Algebra 1. 1. X X 0 0 XX

3.3. X X 1 1 1 1

5.5. X X XX XX

7.7. X X XX ’ ’ 1 1

9.9. ((XX ’)’ ’)’ XX

10.10. X X YY Y Y XX

12.12. XXYYZZ ) ) ( (XXYY ))ZZ

14.14. XXYYZZ ) ) XXY Y XXZZ

16.16. XX YY )) XX YY

2. 2. XX1 1 XX

4.4. XX0 0 0 0

6.6. XXXX XX

8.8. XXXX ’ ’ 0 0

11.11. XXYY YYXX

13.13. XXYYZZ ) ) ( (XXYY ))ZZ

15.15. XXYYZZ ) ) XXYY ))XXZZ ))

17.17. XXYY)’ = )’ = XX YY

commutativecommutative

associativeassociative

distributivedistributive

DeMorgan’s DeMorgan’s

Identities define intrinsic properties of Boolean algebra.Identities define intrinsic properties of Boolean algebra. Useful in simplifying Boolean expressionsUseful in simplifying Boolean expressions Note: 15-17 have no counterpart in ordinary algebra.Note: 15-17 have no counterpart in ordinary algebra. Parallel columns illustrate Parallel columns illustrate duality principleduality principle..

Verifying Identities Using Truth TablesVerifying Identities Using Truth Tables

Can verify any logical equation with small number of variables Can verify any logical equation with small number of variables using truth tables.using truth tables.

Break large expressions into parts, as needed.Break large expressions into parts, as needed.

XXYYZZ ) ) XXYY ))XXZZ ))

YYZZ

00

00

00

11

00

00

00

11

XYZXYZ

000000

001001

010010

011011

100100

101101

110110

111111

XXYYZZ ))

00

00

00

11

11

11

11

11

XXYY

00

00

11

11

11

11

11

11

XXZZ

00

11

00

11

11

11

11

11

XXYY ))XXZZ ))

00

00

00

11

11

11

11

11

XX YY )) XX YY XYXY

0000

0101

1010

1111

XX YY 11

00

00

00

XX YY ))11

00

00

00

DeMorgan’s LawDeMorgan’s Law

DeMorgan’s Laws for DeMorgan’s Laws for nn Variables Variables We can extend DeMorgan’s laws to 3 variables by applying the laws We can extend DeMorgan’s laws to 3 variables by applying the laws

for two variables.for two variables.

((X X Y Y ZZ )) XX Y Y ZZ )))) - by associative law- by associative law

XX Y Y ZZ )) - by DeMorgan’s law- by DeMorgan’s law

XX YY ZZ )) - by DeMorgan’s law- by DeMorgan’s law

XX YY ZZ - by associative law- by associative law

((XXYYZZ)) XXYYZZ )))) - by associative law- by associative law

XX YYZZ )) -- by DeMorgan’s law by DeMorgan’s law

XX YY ZZ )) - by DeMorgan’s law - by DeMorgan’s law

XX YY ZZ - by associative law- by associative law Generalization to Generalization to nn variables. variables.

– ((XX11 + + XX22 + + + + XXnn)) XX 11XX 22 XX nn

– ((XX11XX22 XXnn)) XX 11 + + XX 22 + + + + XX nn

Simplification of Boolean ExpressionsSimplification of Boolean Expressions

F=X YZ +X YZ +XZ

Y

Z

X

Y

Z

X

Y

Z

X

F=X Y(Z +Z )+XZ

by identity 14

F=X Y1+XZ =X Y +XZ by identity 2

by identity 7

The Duality PrincipleThe Duality Principle The The dualdual of a Boolean expression is obtained by interchanging all of a Boolean expression is obtained by interchanging all

ANDANDs and s and ORORs, and all 0s and 1s.s, and all 0s and 1s.– example: the dual of example: the dual of AA+(+(BBCC )+0 is )+0 is AA((BB++CC ))11

The duality principle states that if The duality principle states that if EE11 and and EE22 are Boolean are Boolean

expressions thenexpressions then

EE11= = EE2 2 dualdual ((EE11)=)=dualdual ((EE22))

where where dualdual((EE) is the dual of ) is the dual of EE. For example,. For example,

AA+(+(BBCC )+0 = ()+0 = (BB CC )+)+D D AA((BB++CC ))1 = (1 = (BB ++CC ))DDConsequently, the pairs of identities (1,2), (3,4), (5,6), (7,8), Consequently, the pairs of identities (1,2), (3,4), (5,6), (7,8), (10,11), (12,13), (14,15) and (16,17) all follow from each other (10,11), (12,13), (14,15) and (16,17) all follow from each other through the duality principle.through the duality principle.

The Consensus TheoremThe Consensus TheoremTheoremTheorem. . XYXY + + XX Z Z + +YZ YZ == XY XY + + XX ZZProof.Proof. XYXY + + XX Z Z + +YZ YZ == XY XY + + XX Z Z + + YZYZ((XX + + XX ) 2,7) 2,7

== XY XY + + XX Z Z + + XYZXYZ + + XX YZ YZ 1414

== XY XY + + XYZ XYZ + + XX ZZ + + XX YZ YZ 1010

== XY XY(1 + (1 + ZZ )) + + XX ZZ(1 + (1 + YY ) 2,14) 2,14

== XY XY + + XX Z Z 3,23,2

ExampleExample. . ((A A + + BB )()(AA ++ C C ) = ) = AAAA + + AC AC + + AAB B + + BCBC

== AC AC + + AAB B + + BCBC

== AC AC + + AABB

DualDual. . XX + + YY ))XX + + ZZ ))YY + + ZZ )) = = XX + + YY ))XX + + ZZ ))

Taking the Complement of a FunctionTaking the Complement of a FunctionMethod 1Method 1. Apply DeMorgan’s Theorem repeatedly.. Apply DeMorgan’s Theorem repeatedly.

((XX((YY ZZ + + YZYZ )))) = = XX + (+ (YY ZZ + + YZYZ ))

= = XX + ( + (YY ZZ ))((YZYZ ))

= = XX + (+ (Y Y + + ZZ )()(YY + + ZZ ))

Method 2Method 2. Complement literals and take dual. Complement literals and take dual

((XX ((YY ZZ + + YZYZ ))))= = dualdual ((XX ((YZ YZ + + YY ZZ ))))

= = XX + (+ (Y Y + + ZZ )()(YY + + ZZ ))

Sum of Products FormSum of Products Form The The sum of productssum of products is one of two is one of two standard formsstandard forms for Boolean for Boolean

expressions.expressions.sum-of-products-expressionsum-of-products-expression = = termterm ++ termterm ... ... ++ termterm

termterm = = literalliteral literalliteral literalliteralExample. XExample. X YY ZZ + + XX Z Z + + XY XY + + XYZXYZ

A A mintermminterm is a term that contains every variable, in either is a term that contains every variable, in either complemented or uncomplemented form.complemented or uncomplemented form.

Example. Example. in expression above, in expression above, XX YY ZZ is minterm, but is minterm, but XX ZZ is not is not A A sum of minterms expressionsum of minterms expression is a sum of products expression in is a sum of products expression in

which every term is a mintermwhich every term is a minterm

Example.Example. XX YY ZZ + + XX YZ YZ + + XYZXYZ + + XYZ XYZ is sum of minterms expression that is sum of minterms expression that is equivalent to expression aboveis equivalent to expression above

Product of Sums FormProduct of Sums Form The The product of sumsproduct of sums is the second is the second standard formstandard form for Boolean for Boolean

expressions.expressions.product-of-sums-expressionproduct-of-sums-expression = = s-terms-term s-terms-term ... ... s-terms-term

s-terms-term = = literalliteral literalliteral literalliteralExample. Example. ((XX ++YY ++ZZ )( )(XX ++ZZ )()(XX ++YY )()(XX ++YY ++ZZ ))

A A maxtermmaxterm is a sum term that contains every variable, in is a sum term that contains every variable, in complemented or uncomplemented form.complemented or uncomplemented form.

Example. Example. in exp. above, in exp. above, XX ++YY ++ZZ is a maxterm, but is a maxterm, but XX ++ZZ is not is not A A product of maxterms expressionproduct of maxterms expression is a product of sums expression in is a product of sums expression in

which every term is a maxtermwhich every term is a maxterm

Example.Example. ( (XX ++YY ++ZZ )( )(XX ++YY++ZZ )()(XX++Y+ZY+Z )()(XX++YY++ZZ )) is product of maxterms is product of maxterms expression that is equivalent to expression aboveexpression that is equivalent to expression above

NAND and NOR GatesNAND and NOR Gates

In certain technologies (including CMOS), a NAND (NOR) gate is In certain technologies (including CMOS), a NAND (NOR) gate is simpler & faster than an AND (OR) gate.simpler & faster than an AND (OR) gate.

Consequently circuits are often constructed using NANDs and NORs Consequently circuits are often constructed using NANDs and NORs directly, instead of ANDs and ORs.directly, instead of ANDs and ORs.

Alternative gate representations makes this easier.Alternative gate representations makes this easier.

XY (XY)NAND Gate (XY)X

YNOR Gate

= =

==

Exclusive Or and Odd FunctionExclusive Or and Odd Function

The The oddodd function on function on nn variables is 1 when an odd number of its variables is 1 when an odd number of its variables are 1.variables are 1.– odd(odd(X,Y,ZX,Y,Z ) = ) = XYXY ZZ + + XX YY ZZ + + XX YY ZZ + + XX YY ZZ = = X X Y Y ZZ

– similarly for 4 or more variablessimilarly for 4 or more variables Parity checkingParity checking circuits use the odd function to provide a simple circuits use the odd function to provide a simple

integrity check to verify correctness of data.integrity check to verify correctness of data.– any erroneous single bit change will alter value of odd function, allowing any erroneous single bit change will alter value of odd function, allowing

detection of the changedetection of the change

EXOR gate Alternative Implementation

A

B The EXOR function is defined by The EXOR function is defined by AABB = = ABAB + A + AB.B.

AAB +AB

B

Positive and Negative LogicPositive and Negative Logic In In positive logicpositive logic systems, a high voltage is associated with a logic 1, systems, a high voltage is associated with a logic 1,

and a low voltage with a logic 0.and a low voltage with a logic 0.– positive logic is just one of two positive logic is just one of two conventionsconventions that can be used to associate that can be used to associate

a logic value with a voltagea logic value with a voltage

– sometimes it is more convenient to use the opposite conventionsometimes it is more convenient to use the opposite convention In logic diagrams that use In logic diagrams that use negative logicnegative logic, a , a polarity indicatorpolarity indicator is used is used

to indicate the correct logical interpretation for a signal.to indicate the correct logical interpretation for a signal.

XY XY XY

XY

Circuits commonly use a combination of positive and negative logic.Circuits commonly use a combination of positive and negative logic.

Analysis exampleAnalysis example

Truth tables from logic diagramTruth tables from logic diagram

Logic simulationLogic simulation

Decoder FundamentalsDecoder Fundamentals

Route data to one specific output line.Route data to one specific output line. Selection of devices, resourcesSelection of devices, resources Code conversions.Code conversions. Arbitrary switching functionsArbitrary switching functions

– implements the AND planeimplements the AND plane Asserts one-of-many signal; at most one output will be Asserts one-of-many signal; at most one output will be

asserted for any input combinationasserted for any input combination

EncodingEncoding

BinaryDecimal Unencoded Encoded 0 0001 00 1 0010 01 2 0100 10 3 1000 11

Note: Finite state machines may be unencoded ("one-hot") or binary encoded. If the all 0's state is used, then one less bit is needed and it is called modified one-hot coding.

Why Encode?Why Encode?A Logarithmic RelationshipA Logarithmic Relationship

N

0 25 50 75 100 125 150

Log

2(N)

0

1

2

3

4

5

6

7

8

2:4 Decoder2:4 Decoder

What happens when the inputs goes from 01 to 10?

1 1

1 0

0 1

00D 0D 1

A

B

A

B

A

B

A

B

AND 2

AND 2 A

AND 2 A

AND 2 B

Y

Y

Y

Y

E Q 3

E Q 2

E Q 1

E Q 0

2:4 Decoder with Enable2:4 Decoder with Enable

1 1

1 0

0 1

00

1 1

1 0

0 1

00D 0D 1

ENABLE

A

B

C

AB

C

AB

C

A

B

C

Y

Y

Y

Y

E Q 3

E Q 2

E Q 1

E Q 0

AND 3

AND 3 A

AND 3 A

AND 3 B

2:1 Multiplexer2:1 MultiplexerA

SB

A

B

A

B

Y X1

Y X2

A

BY Y

Design synthesis procedureDesign synthesis procedure

Half AdderHalf Adder

Full Adder – with EXOR, AND and ORFull Adder – with EXOR, AND and OR

Full Adder – with EXOR and NANDFull Adder – with EXOR and NAND

One-bit Full Adder (FA)One-bit Full Adder (FA)

– 3 inputs: A, B, C3 inputs: A, B, C

– 2 outputs: S, Co2 outputs: S, Co

– Truth table:Truth table:

Schematic View:Schematic View:

– cell-based approachcell-based approach

A, B, C S, Co0, 0, 0 0, 00, 0, 1 1, 00, 1, 0 1, 00, 1, 1 0, 11, 0, 0 1, 01, 0, 1 0, 11, 1, 0 0, 11, 1, 1 1, 1

C S

B

ACo

Ripple Carry AdderRipple Carry Adder