Dsl programmable engine for high frequency trading by Heiner Litz et al. (Presented by Pasan De Silva)

DSL Programmable Engine for High Frequency Trading Acceleration

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DSL Programmable Engine for High Frequency Trading

Acceleration

ByHeiner Litz, Christian Leber

& Benjamin Geib

University of Heidelberg

Presenter :– Pasan De Silva

UCSC05 – 12 2013

Authors

Heiner LitzPostdoctoral Research Fellow at Stanford University

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Benjamin GeibPerformance Engineer at IMC financial

markets & asset management

Christian Leber.University of Heidelberg


Basic trading infrastructure

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Exchange

Market Participants

Feed Handler


What is HFT

Describes a set of techniques

within electronic trading of stocks where

a large number of orders are injected into the market

at sub-millisecond round-trip execution times

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HFT

Do not hold significant positions. (On average HFT holds a stock for about 22 seconds)

Generates revenue by buying and selling at a high speed.

Huge Impact !!! Around 73% of the trading volume on the U.S.

equity market is due to HFT. But only 2% of 20 000 firms trade using HFT.

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Strategies of HFT

Cross-market arbitrage Liquidity providing (narrowing the bid

ask spread) makes money out of urgency of sellers

High volatility

All strategies require absolute lowest round trip latencies. Only the fastest HFT

will benefit.

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How to achieve speed

The most time consuming tasks are offloaded in to optimized hardware blocks.

No need to travel through additional stacks. Every thing is handled at hardware level.

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What is FPGAs

Field-Programmable Gate Array, a type of logic chip that can be programmed.

A semiconductor device that can be programmed after manufacturing. Instead of being restricted to any predetermined hardware function, an FPGA allows you to program product features and functions and reconfigure hardware for specific applications even after the product has been installed in the field

FPGAs can be reprogrammed to desired application or functionality requirements after manufacturing.

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FAST protocol

Outstanding orders are made visible to market participants

A feed carrying this information is multicasted to the market participants using standardized protocols and transmitted over UDP over Ethernet

Compression mechanisms to reduce bandwidth introduces significant CPU overhead.

Decoding FAST is a major bottleneck in HFT.

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Proposed approach

Offloading decoding IP, UDP and Eth to optimized hardware blocks

Directly Decode FAST messages in the hardware.

Introduce parallel hardware structures to enable simultaneous decoding of multiple streams.

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Trading Decision making decision to buy or sell a stock, can be a very

complex and resource consuming task.

a variety of given parameters and incoming variables are compared using mathematical and statistical approaches

Due to its complexity, the decision making process is not offloaded to the FPGA but kept in software.

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Trading accelerator architecture

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IP, UDP and ETH decoding in Hardware

To reduce the latency of market data processing decoding of the complete IP, UDP and Ethernet stack is off loaded into hardware.

The Ethernet MAC as well as decoding of the different protocol layers is handled by a number of internal modules.

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FAST decoding in Hardware

FAST decoding has also been offloaded into hardware.

Each feed handler can define own templates. A microcode engine is used that supports a set of

instructions which enables it to decode any variation of the FAST protocol.

microcode is derived from a specification written in a domain specific language (DSL)

DSL is specifically developed for this project. The DSL description is then passed to a compiler

which transforms it into binary microcode that can be executed by the microcode engine.

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Fast decoder

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Optimization baseline implementation provides an

aggregated latency of only 2.6 us to decode the Ethernet, UDP and FAST data stream and transfer it to user space where it can be accessed by software.

But the analysis shows,

D fast realistic > D max

Needs to optimize further.

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Optimization technique 01Custom Instruction Segments.

offer discrete microcode segments, not only for each template but also for each

{TID, PMAP} tuple. Can increase development O/H substantially. Interestingly, only 5 tuples represent a 92%

probability of occurrence. Discrete microcode segments for these tuples

and generic microcode segments for the rest.

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Only five tuples represent a 92% probability of occurrence

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Other optimization techniques

Branch pre calculation

Variable Length Field Processing

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Evaluation improvements. In total, the baseline approach offers a Dmax of

4.8Gbit/s could be improved by over 56% to a new Dmax, optimized of 7.5Gbit/s.

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Multi-threaded Performance Results

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Positives Very useful high end research. Clear language usage Appropriate usage of graphs and images.

Too summarized. Highly complex. Poor related work section. Considerable level of duplications with their original

paper.

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Negatives


Thank you !!!

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Education

Dsl programmable engine for high frequency trading by Heiner Litz et al. (Presented by Pasan De Silva)