Upload
debasis-das
View
3.431
Download
0
Embed Size (px)
DESCRIPTION
This is a presentation on the 8051 micro-controller architecture, instruction set, addressing mo
Citation preview
EI 502Microprocessors
& Microcontrollers
Part 4(Microcontroller 8051)
Debasis Das
Mallabhum Institute of Technology Debasis Das 2
Applications of Microcontrollers
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 3
Simple Interfacing Examples
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 4
Seven segment Interfacing
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 5
Closed loop control system-Temperature control
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 6
Micro-controllers Can be Found in..
Personal information products: Cell phone, pager, watch, pocket recorder, calculator
Laptop components: mouse, keyboard, modem, fax card, sound card, battery charger
Home appliances: door lock, alarm clock, thermostat, air conditioner, TV remote, VCR, small refrigerator, exercise equipment, washer/dryer, microwave oven
Industrial equipment: Temperature/pressure controllers, Counters, timers, RPM Controllers
Toys: video games, cars, dolls, etc.
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 7
Why do we need to learn Microprocessors/controllers?
The microprocessor is the core of computer systems.
Nowadays many communication, digital entertainment, portable devices, are controlled by them.
A designer should know what types of components he needs, ways to reduce production costs and product reliable.
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 8
Why Study MicrocontrollerWill help understand how to
Build useful applications Build programming and debugging skills Understand the insides of a computer
Helps learning computer design, operating systems, compilers, embedded systems, security and other topics.
Microcontrollers have everything in a typical computer: CPU, memory and I/O
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 9
MicrocontrollersEssentially a microprocessor with on-chip
memories and I/O devices
Designed for specific functions
All in one solution - Reduction in chip count
Reduced cost, power, physical size, etc.
Examples
I 8051, MC68332, MC68HC11, PPC555
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 10
Microprocessor CPU is stand-alone, RAM,
ROM, I/O, timer are separate
Designer can decide on the amount of ROM, RAM and I/O ports
expansiveversatile general-purpose
Microcontroller• CPU, RAM, ROM, I/O and
timer are all on a single chip
• Fixed amount of on-chip ROM, RAM, I/O ports
• For applications in which cost, power and space are critical
• Single-purpose
Sep-Oct 2011
Microprocessorvs.
Microcontroller
Mallabhum Institute of Technology Debasis Das 11
Application Areas-Embedded Systems
Special purpose computer system usually completely
inside the device it controls
Has specific requirements and performs pre-defined tasks
Cost reduction compared to general purpose processor
Different design criteria
Performance
Reliability
Availability
Safety
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 12
A Typical Microcontroller
A smaller computerOn-chip RAM, ROM, I/O ports...Example : Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and
PIC 16X
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 13
Typical Resources ona Microprocessor/ControllerCPU: Central Processing UnitI/O: Input /OutputBus: Address bus & Data busMemory: RAM & ROMTimerInterruptSerial PortParallel Port
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 14
Features of 80514K bytes ROM128 bytes RAMFour 8-bit I/O portsTwo 16-bit timersSerial interface64K external code memory space64K data memory space
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 15
Block Diagram
Sep-Oct 2011
CPU
On-chip RAM
On-chip ROM for program code
4 I/O Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
Timer/Counter
Bus Control
TxD RxDP0 P1 P2 P3
Address/Data
Counter Inputs
Mallabhum Institute of Technology Debasis Das 16
Block Diagram
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 17
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7RST
(RXD)P3.0(TXD)P3.1
(T0)P3.4(T1)P3.5
XTAL2XTAL1
GND
(INT0)P3.2(INT1)P3.3
(RD)P3.7(WR)P3.6
VccP0.0(AD0)P0.1(AD1)P0.2(AD2)P0.3(AD3)P0.4(AD4)P0.5(AD5)P0.6(AD6)P0.7(AD7)EA/VPPALE/PROGPSENP2.7(A15)P2.6(A14)P2.5(A13)P2.4(A12)P2.3(A11)P2.2(A10)P2.1(A9)P2.0(A8)
8051
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 18
Pin Description of the 8051
The 8051 is a 40 pin device, but out of these 40 pins, 32 are used for I/O.
24 of these are dual purpose, i.e. they can operate as I/O or a control line or as part of address or date bus.
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 19
MCS-51 “Family” of Microcontollers
Feature 8031 8051 8052 8751 ROM NO 4kB 8kB 4kB UV
Eprom
RAM (Bytes) 128 128 256 128 128
TIMERS 2 2 3 2
I/O PINS 32 32 32 32
SERIAL PORTS 1 1 1 1
INTERRUPT 6 6 8 6 SOURCESSep-Oct 2011
Mallabhum Institute of Technology Debasis Das 20
MCS-51 Family Configurations
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 21
Pins of 8051-1Vcc ( pin 40 ):
Vcc provides supply voltage to the chip. The voltage source is +5V.
GND ( pin 20 ): groundXTAL1 and XTAL2 ( pins 19,18 )
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 22
Pins of 8051-2RST ( pin 9 ): reset
It is an input pin and is active high ( normally low ) .The high pulse must be high at least 2 machine cycles.
It is a power-on reset.Upon applying a high pulse to RST, the microcontroller
will reset and all values in registers will be lost.Reset values of some 8051 registers
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 23
Pins of 8051-3/EA ( pin 31 ): external access
There is no on-chip ROM in 8031 and 8032 .The /EA pin is connected to GND to indicate the code is
stored externally./PSEN & ALE are used for external ROM.For 8051, /EA pin is connected to Vcc.“/” means active low.
/PSEN ( pin 29 ): program store enableThis is an output pin and is connected to the OE pin of the
ROM.
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 24
Pins of 8051-4ALE ( pin 30 ): address latch enable
It is an output pin and is active high.8051 port 0 provides both address and data.The ALE pin is used for de-multiplexing the address and
data by connecting to the G pin of the 74LS373 latch.I/O port pins
The four ports P0, P1, P2, and P3.Each port uses 8 pins.All I/O pins are bi-directional.
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 25
Pins of I/O PortThe 8051 has four I/O ports
Port 0 ( pins 32-39 ): P0 ( P0.0 ~ P0.7 )Port 1 ( pins 1-8 ) : P1 ( P1.0 ~ P1.7 )Port 2 ( pins 21-28 ): P2 ( P2.0 ~ P2.7 )Port 3 ( pins 10-17 ): P3 ( P3.0 ~ P3.7 )Each port has 8 pins.
Named P0.X ( X=0,1,...,7 ) , P1.X, P2.X, P3.XEx : P0.0 is the bit 0 ( LSB ) of P0 Ex : P0.7 is the bit 7 ( MSB ) of P0These 8 bits form a byte.
Each port can be used as input or output (bi-direction).
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 26
Other PinsP1, P2, and P3 have internal pull-up resisters.
P1, P2, and P3 are not open drain.P0 has no internal pull-up resistors and does not
connects to Vcc inside the 8051.P0 is open drain.Compare the figures of P1.X and P0.X. However, for a programmer, it is the same to
program P0, P1, P2 and P3.All the ports upon RESET are configured as output.
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 27
Port 3 Alternate Functions
Sep-Oct 2011
17RDP3.7
16WRP3.6
15T1P3.5
14T0P3.4
13INT1P3.3
12INT0P3.2
11TxDP3.1
10RxDP3.0
PinFunctionP3 Bit
Mallabhum Institute of Technology Debasis Das
28
8051 Register Contents on Reset
Sep-Oct 2011
0000DPTR
0007SP
0000PSW
0000B
0000ACC
0000PC
Reset ValueRegister
Mallabhum Institute of Technology Debasis Das 29
Memory mapping in 8051
Sep-Oct 2011
0000H
0FFFH
0000H
1FFFH
0000H
7FFFH
8751AT89C51 8752
AT89C52
DS5000-32
ROM memory map in 8051 family
from Dallas Semiconductor
from Atmel Corporation
4k 8k 32k
Mallabhum Institute of Technology Debasis Das 30Sep-Oct 2011
RAM memory space allocation in the 8051
7FH
30H
2FH
20H
1FH
17H
10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack ) 1Register Bank
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
RAM Address Space
Mallabhum Institute of Technology Debasis Das 31
Stack in the 8051The register used to
access the stack is called SP (stack pointer) register.
The stack pointer in the 8051 is only 8 bits wide, which means that it can take value 00 to FFH. When 8051 powers up, the SP register contains value 07.
7FH
30H
2FH
20H1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
)Stack (Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 32Sep-Oct 2011
Timer Modes
Mallabhum Institute of Technology Debasis Das 33
Timer Modes
Gate : When set, timer only runs while INT(0,1) is high.C/T : Counter/Timer select bit.M1 : Mode bit 1.M0 : Mode bit 0.
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 34
Interrupt
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 35
8051 CPU Registers
Sep-Oct 2011
A (8-bit Accumulator)
B (8-bit register for Mul &Div)
PSW (8-bit Program Status Word)
SP (8-bit Stack Pointer)
PC (16-bit Program Counter)
DPTR (16-bit Data Pointer)
Mallabhum Institute of Technology Debasis Das 36
Special Function Registers
Sep-Oct 2011
DATA registers
CONTROL registers
•Timers
•Serial ports
•Interrupt system
•Analog to Digital converter•Digital to Analog converter etc.. Addresses 80h – FFH
Direct Addressing is used to access SFRs
Mallabhum Institute of Technology Debasis Das 37
Registers
Sep-Oct 2011
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bit Registers of the
8051
Mallabhum Institute of Technology Debasis Das 38
List of Registers(*Denotes the SFRs)
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 39
Contd…
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 40
PSW REGISTER
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 41
Memory mapping in 8051
ROM memory map in 8051 family
0000H
0FFFH
0000H
1FFFH
0000H
7FFFH
80518752
4k
DS5000-32
8k 32k
from Atmel Corporation
from Dallas Semiconductor
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 42
7FH
30H
2FH
20H
1FH
17H
10H
0FH
07H
08H
18H
00HRegister Bank 0
)Stack (Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
RAM Memory Space Allocation in the 8051
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 43
Address Multiplexing for External Memory
Sep-Oct 2011
Accessing external
code memory
Mallabhum Institute of Technology Debasis Das 44
Accessing External Data Memory
Sep-Oct 2011
Interface to 1K
RAM
Mallabhum Institute of Technology Debasis Das 45
Ports of 80518051 has 4 Ports. Port 0, Port1, Port2 , Port3
Sep-Oct 2011
Port 0 is a dual purpose port, it is located from pin 32 to pin 39 (8 pins). To use this port as both input/output ports each pin must be connected externally to a 10 k ohm pull-up resistor. This is because Port 0 is an open drain.
Simple ex: MOV A, #22
BACK MOV P0 ,A
ACALL DELAY
CPL A
SJMP BACK
Mallabhum Institute of Technology Debasis Das 46
Ports of 8051Port 1 is a dedicated I/O port from pin 1 to pin 8. Upon reset it is
configured as out port. It is generally used for interfacing to
external device thus if you need to connect to switches or LEDs,
you could make use of these 8 pins, but it doesn’t need any
pull-up resistors (internal)
Like port 0, port 2 is a dual-purpose port.(Pins 21 through 28) It
can alternately be used as the high byte of the address bus for
designs with external code memory. Port2 also doesn’t require
any pull-up resistors
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 47
Ports of 8051Port 3 is also dual purpose but designers generally avoid
using this port unnecessarily for I/O because the pins have
alternate functions which are related to special features of
the 8051.
For a programmer, it is the same to program P0, P1, P2
and P3.
All the ports upon RESET are configured as output. To
use any of the ports as an input port.Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 48
Alternative Definitions of Port 3
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 49
Timers /Counters The 8051 has 2 timers/counters:
Timer/Counter 0 Timer/Counter 1
They can be used as
1. A Timer to be a time delay generator, internal clock is used
2. An event counter External signals from input pin counted for number of
events on registers These clock pulses could help count people through a
gate, or number of wheel rotations, or any other event that can be converted to pulses
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 50
Timer Set the initial value of registersStart the timer, the 8051 counts upInput from internal system clockWhen the registers equals 0, the 8051 sets
a bit to denote time out
Sep-Oct 2011
toLCD
P1
8051
TL0
TH0
P2SetTimer 0
Mallabhum Institute of Technology Debasis Das 51
CounterCount number of events
Show number of events on registersExternal input to T0 input pin (P3.4) for Counter 0External input to T1 input pin (P3.5) for Counter 1
Sep-Oct 2011
T0
toLCD
P3.4
P1
8051
a switch
TL0
TH0
Mallabhum Institute of Technology Debasis Das 52
Registers Used in Timer/Counter
8051 has two 16-bit Timer registers ,Timer 0 & Timer 1.
As 8051 has 8-bit architecture , each Timer register is treated as two 8-bit registers namely
TH0, TL0, TH1, TL1. One 8-bit mode register -TMOD.One 8-bit control register-TCON.
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 53
TMOD Register
Both Timer 0 &Timer 1 use the same Mode register TMOD.
It is an-8-bit register .The lower 4-bits are meant for Timer 0 &the upper 4-bits are meant for Timer 1
It is not bit addressable, used like any other register of 8051 . For ex: MOV TMOD,#21H
Sep-Oct 2011
GATE C/T M1 M0 GATE C/T M1 M0Timer 1 Timer 0
(MSB) (LSB)
Mallabhum Institute of Technology Debasis Das 54
TMOD-Gate OperationClock to timers can be gated
GATE=0 Internal control Software starts and stops the timer Set/clear TR for start/stop timer. SETB TR0 CLR TR0
GATE=1 External control An external control helps start or stopTimer/counter is enabled only while the INT pin is high and the
TR control pin is set (TR).
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 55
TMOD Controls
C/T : Timer or counter selected cleared for timer operation (input from internal system clock). Set for counter operation (input from Tx input pin).
M1,M0 : Used for mode selection.
M1 M0 Mode Operation
0 0 0 13-bit timer mode 8-bit THx + 5-bit TLx (x= 0 or
0 1 1 16-bit timer mode 8-bit THx + 8-bit TLx 1 0 2 8-bit auto reload 8-bit auto reload tim/cntr THx holds a value which is to be reloaded into TLx each time it overflows.
1 1 3 Split timer mode
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 56
Sep-Oct 2011
TCON Register
Timer control register TMOD is a 8-bit
register which is bit addressable and in
which Upper nibble is for timer/counter,
lower nibble is for interrupts
Mallabhum Institute of Technology Debasis Das 57Sep-Oct 2011
8051- SERIAL COMMUNICATION
Mallabhum Institute of Technology Debasis Das 58
Basics of serial communication
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 59
Types of Serial communications
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 60
RxD and TxD pins in the 8051The 8051 has two pins for transferring and receiving
data by serial communication. These two pins are part of the Port3(P3.0 &P3.1)
These pins are TTL compatible and hence they require a line driver to make them RS232 compatible
Max232 chip is one such line driver in use. Serial communication is controlled by an 8-bit
register called SCON register, it is a bit addressable register.
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 61
Serial Control RegisterSCON
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 62
SCON Mode SettingThese two bits of SCON register determine
number of bits per character, start bit and stop bits.
SM0 SM1
0 0 Serial Mode 0
0 1 Serial Mode 1, 8 bit data,
1 stop bit, 1 start bit
1 0 Serial Mode 2
1 1 Serial Mode 3
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 63
Receive EnableREN (Receive Enable)-When high, allows 8051 to
receive data on the RxD pin. When low the receiver is disabled. This is achieved as below
SETB SCON.4
& CLR SCON.4
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 64
Transmit & Receive Interrupts
TI (Transmit interrupt)- TI is raised when a byte is completely transmitted. The TI bit is raised at the beginning of the stop bit.
RI (Receive interrupt)- once a byte is completely received, it is transferred to SBUF and the interrupt is raised.
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 65
Interrupt VectorsExternal Interrupt 0: 0003hTimer 0 overflow: 000BhExternal Interrupt 1: 0013hTimer 1 overflow: 001BhSerial : 0023hTimer 2 overflow(8052+) 002bh
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 66
Interrupt Enable Register
Upon reset all Interrupts are disabled
These interrupts must be enabled
This is done through an Interrupt Enable
Register (IE).
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 67
EA : Global enable/disable.--- : Undefined.ET2 : Enable Timer 2 interrupt.ES : Enable Serial port interrupt.ET1 : Enable Timer 1 interrupt.EX1 :Enable External 1 interrupt.ET0 : Enable Timer 0 interrupt. EX0 : Enable External 0 interrupt.
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 68
Interrupt Priorities All interrupts have a power on default priority
order. 1. External interrupt 0 (INT0)2. Timer interrupt0 (TF0)3. External interrupt 1 (INT1)4. Timer interrupt1 (TF1)5. Serial communication (RI+TI)
Priority can also be set to “high” or “low” by IP register
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 69
Interrupt Priorities Register
IP.7: reserved
IP.6: reserved
IP.5: Timer 2 interrupt priority bit (8052 only)
IP.4: Serial port interrupt priority bit
IP.3: Timer 1 interrupt priority bit
IP.2: External interrupt 1 priority bit
IP.1: Timer 0 interrupt priority bit
IP.0: External interrupt 0 priority bitSep-Oct 2011
--- PX0PT0PX1PT1PSPT2---
Mallabhum Institute of Technology Debasis Das 70
EPROM Programming
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 71
Program Verification
Sep-Oct 2011
The 8051 Assembly Language
Mallabhum Institute of Technology Debasis Das 73
Instruction Set
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 74
Sample Memory Organization
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 75
Internal Data Memory
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 76
Special FunctionRegisters
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 77
Addressing Modes
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 78
Register Addressing
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 79
Direct Addressing
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 80
Indirect Addressing
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 81
Immediate Constant Addressing
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 82
Relative Addressing
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 83
Absolute Addressing
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 84
Long Addressing
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 85
Indexed Addressing
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 86
Instruction Types
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 87
Arithmetic Operations
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 88
Logical Operations
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 89
Data Transfer Operations
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 90
Boolean Operations
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 91
Program Branching Operations
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 92
Arithmetic InstructionsAddSubtractIncrementDecrementMultiplyDivide Decimal adjust
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das
93
Arithmetic Instructions
Mnemonic Description
ADD A, byte add A to byte, put result in A
ADDC A, byte add with carry
SUBB A, byte subtract with borrow
INC A increment A
INC byte increment byte in memory
INC DPTR increment data pointer
DEC A decrement accumulator
DEC byte decrement byte
MUL AB multiply accumulator by b register
DIV AB divide accumulator by b register
DA A decimal adjust the accumulator
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 94
ADD Instructionsadd a, byte ; a a + byteaddc a, byte ; a a + byte + CThese instructions affect 3 bits in PSW:
C = 1 if result of add is greater than FF
AC = 1 if there is a carry out of bit 3
OV = 1 if there is a carry out of bit 7, but not from bit 6, or visa versa.
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 95
Instructions that Affect PSW bits
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 96
Increment and Decrement
The increment and decrement instructions do NOT affect the C flag.
Notice we can only INCREMENT the data pointer, not decrement.
Sep-Oct 2011
INC A increment A
INC byte increment byte in memory
INC DPTR increment data pointer
DEC A decrement accumulator
DEC byte decrement byte
Logic Instructions
Bitwise logic operations (AND, OR, XOR, NOT)
Clear
Rotate
Swap
Logic instructions do NOT affect the flags in PSW
Mallabhum Institute of Technology Debasis Das 98
Program Flow Control
Unconditional jumps (“go to”)
Conditional jumps
Call and return
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 99
Call and Return
Call is similar to a jump, butCall pushes PC on stack before branching
acall <address ll> ; stack PC ; PC address 11 bit
lcall <address 16> ; stack PC ; PC address 16 bit
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 100
An Example Subroutinesquare: push b
mov b,a mul ab
pop b ret
8 byte and 11 machine cycle
square: inc a movc a,@a+pc ret
table: db 0,1,4,9,16,25,36,49,64,81
13 byte and 5 machine cycle
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 101
Another Subroutine Example
; Program to compute square root of value on Port 3 ; (bits 3-0) and output on Port 1.
org 0ljmp Main
Main: mov P3, #0xFF ; Port 3 is an inputloop: mov a, P3
anl a, #0x0F ; Clear bits 7..4 of Alcall sqrtmov P1, asjmp loop
sqrt: inc amovc a, @a + PCret
Sqrs: db 0,1,1,1,2,2,2,2,2,3,3,3,3,3,3,3 end
Sep-Oct 2011
reset service
main program
subroutine
data
Mallabhum Institute of Technology Debasis Das 102
Subroutines Help!
Subroutines allow us to have "structured" assembly language programs.
This is useful for breaking a large design into manageable parts.
It saves code space when subroutines can be called many times in the same program.
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 103
Example of Delay
Sep-Oct 2011
mov a,#0aahBack1:mov p0,a
lcall delay1cpl asjmp back1
Delay1:mov r0,#0ffh;1cycleHere: djnz r0,here ;2cycle
ret ;2cycleend
Delay=1+255*2+2=513 cycle
Delay2: mov r6,#0ffhback1: mov r7,#0ffh ;1cycleHere: djnz r7,here ;2cycle djnz r6,back1;2cycle
ret ;2cycle
end
Delay=1+(1+255*2+2)*255+2 =130818 machine cycle
Mallabhum Institute of Technology Debasis Das 104
Long delay GREEN_LED: equ P1.6
org oohljmp Main
org 100h
Main: clr GREEN_LED
Again: acall Delay cpl GREEN_LED sjmp Again
Delay: mov R7, #02Loop1: mov R6, #00hLoop0: mov R5, #00h
djnz R5, $
djnz R6, Loop0
djnz R7, Loop1
ret
END
Sep-Oct 2011
reset service
main program
subroutine
Mallabhum Institute of Technology Debasis Das 105
String Operations; Move string from code memory to RAM
org 0mov dptr,#stringmov r0,#10h
Loop1: clr amovc a,@a+dptrjz stopmov @r0,ainc dptrinc r0sjmp loop1
Stop: sjmp stop
; on-chip code memory used for stringorg 18h
String: db ‘this is a string’,0end
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 106
Strobed I/O; p0:input p1:output
mov a,#0ffhmov p0,a
back: mov a,p0mov p1,asjmp back
setb p1.2mov a,#45h ;data
Again: jnb p1.2,again ;wait for data request
mov p0,a ;enable strobesetb p2.3clr p2.3
Sep-Oct 2011
Mallabhum Institute of Technology Debasis Das 107
Interrupts
Sep-Oct 2011
…mov a, #2mov b, #16mul abmov R0, amov R1, bmov a, #12mov b, #20mul abadd a, R0mov R0, amov a, R1addc a, bmov R1, aend
Program
Execution
interrupt
ISR: inc r7 mov a,r7 jnz NEXT
cpl P1.6 NEXT: reti
return