CSC 222: Computer Organization

& Assembly Language

6 - Interrupts Handling

Basic Instruction Cycle

Fetch Decode Execute

Fetch

1. Fetch an instruction from memory

2. Decode the instruction to determine the operation

3. Fetch data from memory if necessary

Execute

4. Perform the operation on the data

5. Store the result in memory if needed

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Instruction Cycle State Diagram

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Contd..

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Instruction Fetch Read instruction from memory into processor

Instruction Operation Decoding Determine the type of operation to be performed and operand(s) to

be used.

Operand Address Calculation If operation involves reference to an operand in memory or I/O, then

determine the address of operand.

Operand Fetch Fetch from memory or read from I/O

Data Operation Perform the operation

Operand Store Write into memory or out to I/O if required

Interrupts – Changing Program Flow

Mechanism by which other modules (e.g. I/O) may interrupt

normal sequence of processing

Hardware interrupts

Hardware devices to interrupt the processor for some I/O

operation.

Software interrupts

Sent by programs to request system services.

Sent by programs using the INT instruction.

Handling follows a similar procedure to hardware interrupts.

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Interrupts…

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Processor exception

System generated interrupts

Occurs when some condition arises in the processor which

requires special handling.

Each exception has a unique handling number

Interrupt Cycle

Added to instruction cycle

Processor checks for interrupt

Indicated by an interrupt signal

If no interrupt, fetch next instruction

If interrupt pending:

Suspend execution of current program

Save context

Set PC to start address of interrupt handler routine

Process interrupt

Restore context and continue interrupted program

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Transfer of Control via Interrupts

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Instruction Cycle with Interrupts

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Instruction Cycle (with Interrupts) - State Diagram

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Multiple Interrupts

Disable interrupts

Processor will ignore further interrupts while processing one

interrupt

Interrupts remain pending and are checked after first interrupt

has been processed

Interrupts handled in sequence as they occur

Define priorities

Low priority interrupts can be interrupted by higher priority

interrupts

When higher priority interrupt has been processed, processor

returns to previous interrupt

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Multiple Interrupts - Sequential

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Multiple Interrupts – Nested

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Chapter Reading

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Chapter 3, William Stallings, “Computer Organization

& Architecture”