1.ARM LPC2148 SCI BlockProf. Anish Goel

2. UUART Features 16 byte Receive and Transmit FIFOs Register locations conform to 550 industrystandard. Receiver FIFO trigger points at 1, 4, 8, and 14bytes. Built-in fractional baud rate generator withautobauding capabilities. Mechanism that enables software and hardwareflow control implementation.2LPC2148 UART Prof. Anish Goel 3. Pin description3LPC2148 UART Prof. Anish Goel 4. Register description4LPC2148 UART Prof. Anish Goel 5. UART0 Receiver Buffer Register The U0RBR is the top byte of the UART0 Rx FIFO. Thetop byte of the Rx FIFO contains the oldest characterreceived and can be read via the bus interface. The LSB (bit 0) represents the oldest received data bit.If the character received is less than 8 bits, the unusedMSBs are padded with zeroes.5 LPC2148 UART Prof. Anish Goel 6. UART0 Transmit Holding Register The U0THR is the top byte of the UART0 TX FIFO. Thetop byte is the newest character in the TX FIFO and canbe written via the bus interface. The LSB represents the first bit to transmit.6LPC2148 UART Prof. Anish Goel 7. UART0 Divisor Latch Registers The UART0 Divisor Latch is part of the UART0 FractionalBaud Rate Generator and holds the value used to divide theclock supplied by the fractional prescaler in order to producethe baud rate clock, which must be 16x the desired baud rate . The U0DLL and U0DLM registers together form a 16 bitdivisor where U0DLL contains the lower 8 bits of the divisorand U0DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001 value as division byzero is not allowed. The Divisor Latch Access Bit (DLAB) in U0LCR must be onein order to access the UART0 Divisor Latches.7LPC2148 UART Prof. Anish Goel 8. UART0 Divisor Latch Registers8 LPC2148 UART Prof. Anish Goel 9. UART0 Fractional Divider Register The UART0 Fractional Divider Register (U0FDR)controls the clock pre-scaler for the baud rate generationand can be read and written at users discretion. This pre-scaler takes the APB clock and generates anoutput clock per specified fractional requirements.9LPC2148 UART Prof. Anish Goel 10. Baud Rate CalculationWhere PCLK is the peripheral clock, U0DLM and U0DLL are the standard UART0 baud rate divider registers, and DIVADDVAL and MULVAL are UART0 fractional baudrate generator specific parameters.[Refer Section 10.3.5 of UM2148 for standard baudrate calculation]10 LPC2148 UART Prof. Anish Goel 11. UART0 Interrupt Enable RegisterThe U0IER is used to enable UART0 interrupt sources.11 LPC2148 UART Prof. Anish Goel 12. UART0 Interrupt Enable Register12LPC2148 UART Prof. Anish Goel 13. UART0 Interrupt Identification RegisterThe U0IIR provides a status code that denotes the priority and source of a pending interrupt.The interrupts are frozen during an U0IIR access. If an interrupt occurs during an U0IIR access, the interrupt is recorded for the next U0IIR access.13 LPC2148 UART Prof. Anish Goel 14. UART0 Interrupt Identification Register14LPC2148 UART Prof. Anish Goel 15. UART0 FIFO Control RegisterThe U0FCR controls the operation of the UART0 Rx and TX FIFOs.15LPC2148 UART Prof. Anish Goel 16. UART0 Line Control RegisterThe U0LCR determines the format of the data character that is to be transmitted or received.16 LPC2148 UART Prof. Anish Goel 17. UART0 Line Status Register17LPC2148 UART Prof. Anish Goel 18. UART0 Line Status Register18LPC2148 UART Prof. Anish Goel 19. UART0 Line Status Register19LPC2148 UART Prof. Anish Goel 20. UART0 Scratch pad registerThe U0SCR has no effect on the UART0 operation. This register can be written and/or read at users discretion.There is no provision in the interrupt interface that would indicate to the host that a read or write of the U0SCR has occurred.20 LPC2148 UART Prof. Anish Goel 21. UART0 Auto-baud Control Register21LPC2148 UART Prof. Anish Goel 22. UART0 Transmit Enable RegisterThe U0TER enables implementation of software flow control. When TXEn=1, UART0 transmitter will keep sending data as long as they are available.As soon as TXEn becomes 0, UART0 transmission will stop.22 LPC2148 UART Prof. Anish Goel 23. ArchitectureThe architecture of the UART0 is shown below in the block diagram.The APB interface provides a communications link between the CPU or host and the UART0.The UART0 receiver block, U0RX, monitors the serial input line, RXD0, for valid input.The UART0 RX Shift Register (U0RSR) accepts valid characters via RXD0. After a valid character is assembled in the U0RSR, it is passed to the UART0 RX Buffer Register FIFO to await access by the CPU or host via the generic host interface.23LPC2148 UART Prof. Anish Goel 24. ArchitectureThe UART0 transmitter block, U0TX, accepts data written by the CPU or host and buffers the data in the UART0 TX Holding Register FIFO (U0THR).The UART0 TX Shift Register (U0TSR) reads the data stored in the U0THR and assembles the data to transmit via the serial output pin, TXD0.The UART0 Baud Rate Generator block, U0BRG, generates the timing enables used by the UART0 TX block. The U0BRG clock input source is the APB clock (PCLK).The main clock is divided down per the divisor specified in the U0DLL and U0DLM registers.This divided down clock is a 16x oversample clock, NBAUDOUT.24LPC2148 UART Prof. Anish Goel 25. The interrupt interface contains registers U0IER and U0IIR. The interrupt interface receives several one clock wide eStatus information from the U0TX and U0RX is stored in the U0LSR. Control information for the U0TX and U0RX is stored in the U0LCR. Enables from the U0TX and U0RX blocks.25LPC2148 UART Prof. Anish Goel 26. UART0 block diagram26LPC2148 UART Prof. Anish Goel