• The McBSP consists of a data path and a control path that connect to external devices.

• Separate pins for transmission and reception communicate data to these external devices.

• Four other pins communicate control information (clocking and frame synchronization).

• The device communicates to the McBSP using 32-bit-wide control and data registers accessible via the internal peripheral bus.

Pin Description

CLKR Receive clockCLKX Transmit clockCLKS External clockDR Received serial dataDX Transmitted serial dataFSR Receive frame synchronizationFSX Transmit frame synchronization

• CPU or DMA write the DATA to be transmitted to the Data transmit register (DXR) which is shifted out to DX via the transmit shift register (XSR).

• Similarly, receive data on the DR pin is shifted into the receive shift register (RSR) and copied into the receive buffer register (RBR).

• RBR is then copied to DRR, which can be read by the CPU or the DMA controller.

• This allows internal data movement and external data communications simultaneously.

• The following control registers are used in multichannel operation:• The multi channel control register (MCR)• The transmit channel enable register (XCER)• The receive channel enable register (RCER)

• Other registers for clock generation, frame synchronization and control are:

• serial port control register (SPCR)• receive control register (RCR)• transmit control register (XCR)• pin control register (PCR)• Sample rate generator register (SRGR)