Program storage Boot ROM for personal computers Complete application storage for embedded systems.

Modern chips use transistors to pull down lines:

EEPROM:

a.k.a. “RAM” (Random Access Memory) Volatility

Most RAMs lose their memory when power is removed

NVRAM = RAM + battery Or use EEPROM

SRAM (Static RAM) Memory behaves like latches or flip-flops

DRAM (Dynamic Memory) Memory lasts only for a few milliseconds Must “refresh” locations by reading or writing

Individual bits are D latches, not edge-triggered D flip-flops. Fewer transistors per cell.

Implications for write operations: Address must be stable before writing cell. Data must be stable before ending a write.

Chip select Output enable Write enable

Similar to ROM read timing

Address must be stable before and after write-enable is asserted.

Data is latched on trailing edge of (WE & CS).

Use the same data pins for reads and writes Especially common on wide devices Makes sense when used with microprocessor

buses (also bidirectional)

load MAR from bus appears

load MAR from bus disappearsOE_L asserted

load MBR from memory appears

load MBR disappearsOE_L disappears

MAR has memory address MBR has data

memory read (assuming CS_L is always asserted):

load MAR from bus appears

load MBR from bus appearsenable MBR to memory appearsload MAR from BUS disappears

WE_L appears

WE_L disappears

MAR has memory address

MBR has data

memory write (assuming CS_L is always asserted):

load MBR disappears

Similar to ROM packages

28-pin DIPs 32-pin DIPs

Use latch-type SRAM cells internally

Put registers in front of address and control (and maybe data) for easier interfacing with synchronous systems at high speeds

E.g., Pentium cache RAMs

SRAMs typically use six transistors per bit of storage.

DRAMs use only onetransistor per bit:

1/0 = capacitorcharged/discharged

Precharge bit line to VDD/2. Take the word line HIGH. Detect whether current flows into or out of the

cell. Note: cell contents are destroyed by the read! Must write the bit value back after reading.

Take the word line HIGH. Set the bit line LOW or HIGH to store 0 or 1. Take the word line LOW.

Note: The stored charge for a 1 will eventually leak off.

Typical devices require each cell to be refreshed once every 4 to 64 mS.

During “suspended” operation, notebook computers use power mainly for DRAM refresh.

64K x 1DRAM

multiplex 16-bit addressas 8-bit row selectorand 8-bit column selector

Row Address Strobe, Column Address Strobe n address bits are provided in two steps using n/2 pins, referenced to the falling edges of RAS_L and CAS_L

Traditional method of DRAM operation for 20 years.

Now being supplanted by synchronous, clocked interfaces in SDRAM (synchronous DRAM).

DRAM read timing