Challenges of Parallel Simulation of Power Systems_english

www.opal-rt.com

Ould Bachir, TarekJanuary 8th, 2015

Challenges of Parallel Simulation of

Power Systems

http://www.opal-rt.com

22

Outline

1 2 3 4

Introduction Challenges

Large Nerworks

Problematic

33

Outline

1 2 3 4


Large Nerworks

Problematic

44

Power System Simulation

Introduction

Network Simulation Controller Prototyping

Transients Analysis Fault Scenarios

55

Power System Simulation

ePHASORsimReal-Time TransientStability Simulator10 ms time step

HYPERsimLarge Scale Power SystemSimulation for Utilities & Manufacturers25 µs to 100 µs time step

eFPGAsimPower Electronics Simulation on FPGA1 µs to 100 ns time step

1 s(1 Hz)

10,000

2,000

1,000

500

100

10

0

10 ms(100 Hz)

50 µs(20 KHz)

10 µs(100 KHz)

1µs(1 MHz)

100 ns(10 MHz)

10 ns(100 MHz)

20,000

Transients Period (frequency)

Number of buses

eMEGAsimPower System & Power Electronics SimulationBased on Matlab/Simulink and SimPowerSystems10 µs to 100 µs time step

Introduction

Phase Domain

Time Domain

66

Introduction

The

Host

Controller

Real-Time Simulator

77

Introduction

15-20 years ago, the revolution was to build simulators from off-the-shelf PC (PCs were connected in clusters)

HIL Simulators

OP5607 (Virtex 7)

OP4500 (Kintex 7)

CPU computing power is often insufficient, hence FPGA are often used to offload part or total of computing load

88

Outline

1 2 3 4


Large Nerworks

Problematic

99

Problematic

In HIL simulation, a real hardware (i.e. a physical controller) is connected to the simulator. The simulation loop must be as fast as possible!

Simulated plantPhysical controller

PWM pulse

Analog V/I Hall Effect

1010

Problematic

• Advances in semiconductor technology allow very high switching frequencies (10kHz to 100kHz) to be reached

• Such frequencies have various benefits for the power system: higher power density, lower THD, etc.

• They are however very challenging for real-time simulatorsthat must achieve time steps below 1 μs

0 5 10 15 20-0.5

0

0.5

1

1.51 kHz PWM (UA)

Logic

level

Time (ms)

0 5 10 15 20

-20

0

20

Load currents

Curr

ent

(A)

Time (ms)

0 5 10 15 20-0.5

0

0.5

1

1.520 kHz PWM (UA)

Logic

level

Time (ms)

0 5 10 15 20

-20

0

20

Load currents

Curr

ent

(A)

Time (ms)

0 5 10 15 20-0.5

0

0.5

1

1.51 kHz PWM (UA)

Logic

level

Time (ms)

0 5 10 15 20

-20

0

20

Load currents

Curr

ent

(A)

Time (ms)

0 5 10 15 20-0.5

0

0.5

1

1.520 kHz PWM (UA)

Logic

level

Time (ms)

0 5 10 15 20

-20

0

20

Load currents

Curr

ent

(A)

Time (ms)

1111

Problematic

• To meet such tight timing requirements, FPGA-based real-time simulation has proven to be an effective solution (the only one in fact!)

• However, solving differential algebraic equations (DAEs) on FPGA means designing an application specific processor (ASP) from scratch!

Physical controller

PWM pulse

Simulated plant

FPGA

1212

Outline

1 2 3 4


Large Nerworks

Problematic

1313

Challenges

• Technical challenges:• Number format: Floating-Point (FP) vs. Fixed-Point (FXP)• FP Operators have long latencies• Clock Frequency: how to increase it with minimal impact on the latency• How to model power converters (switched networks)

• Practical challenges:• FPGA programming is tedious and requires special skills (end user is a

power electronics specialist)• Programming and reprogramming times are long: objective is to avoid the

penalty on prototyping

1414

Solutions to technical challenges

• Self-Alignement technique

1515


• High Radix Carry Save (HRCS) used to reduce latency of the FP operators

1616


• Custom operators with fused-path

1717

Solutions to practical challenges

1818


• Architecture of the computing engine

Blocks RAM, CPU reprogrammable

1919


Workflow

Host Computer(Console)

Design Power Electronics Circuit

Real-TimeSimulator

Execute the CPU Model

FPGA

Execute the power converter model on FPGA

No hardware design

skills required

No reprogramming

No bitstream generation

Physical controller

HIL Simulation

2020

Outline

1 2 3 4


Large Nerworks

Problematic

2121

Large networks simulation

HVDC Transmission System

MMC 2MMC 1

1GW

± 320 kV

C = 10mF

Larm = 50mH

C = 10mF

Larm = 50mHBypass

breaker 1

Rstart = 100Ω

Bypass

breaker 2

Rstart = 100Ω 70 km DC cable

1 2 12

Main ac

breaker 1

Main ac

breaker 2

AC EQ.

SRC1

AC EQ.

SRC2

CPU #1:

Eq. Source no 1CPU #2: VSC-MMC Station no. 1 CPU #3: VSC-MMC Station no. 2

CPU #4:

Eq. Source no 2

Low Level

Control

CPU #6: Inverter Control

Upper Level

Control

Upper Level

Control

CPU #5: Rectifier Control

Low Level

Control

MMC ConvertersSimulated on FPGA

2222


MMC Structure

400 SM

eq. 9600 semi-conducteurs

MMC Computing Engine Architecture

2323

0 0.5 1 1.5 2 2.5 3 3.5-0.2

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

vua(p

u)

time (s)

0 0.5 1 1.5 2 2.5 3 3.5-4

-3

-2

-1

0

1

2

3

4

5

i ua(p

u)

time (s)

0 0.5 1 1.5 2 2.5 3 3.50

5

10

15

20

25

30

35

Vc

tot

up A

(pu)

time (s)

CPU MMC

FPGA MMC


Perfect match with the offline simulation reference

2424

0 0.5 1 1.5 2 2.5 3 3.5-0.2

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

vua(p

u)

time (s)

0 0.5 1 1.5 2 2.5 3 3.5-4

-3

-2

-1

0

1

2

3

4

5

i ua(p

u)

time (s)

0 0.5 1 1.5 2 2.5 3 3.50

5

10

15

20

25

30

35

Vc

tot

up A

(pu)

time (s)

CPU MMC

FPGA MMC



2525

2.44 2.46 2.48 2.5 2.52 2.54 2.56

0

0.2

0.4

0.6

0.8

1

1.2

vua(p

u)

time (s)

2.45 2.46 2.47 2.48 2.49 2.5 2.51 2.52 2.53 2.54 2.55-1.2

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

i ua(p

u)

time (s)

2.45 2.46 2.47 2.48 2.49 2.5 2.51 2.52 2.53 2.54 2.55370

380

390

400

410

420

430

440

450

Vc

tot

up A

(pu)

time (s)

CPU HVDC

FPGA HVDC



2626

Thank you for your kind attention.

www.opal-rt.com

Acta est fabula

Contact:

Tarek Ould Bachir

R&D Engineer

[email protected]

Opal-RT Technologies

Engineering

Challenges of Parallel Simulation of Power Systems_english