Combinational Circuits

Combinational Circuits

CS2052 Computer Architecture

Computer Science & Engineering

University of Moratuwa

Dilum [email protected]

Blocks of a Microprocessor

2

Literal

Address

Operation

Program

Memory

Instruction

Register

STACK Program CounterInstruction

Decoder

Timing, Control and Register selection

Accumulator

RAM &

Data

Registers

ALU

IO

IOFLAG &

Special

Function

Registers

Clock

Reset

Interrupts

Program Execution Section Register Processing Section

Set upSet up

Modify

Address

Internal data bus

Source: Makis Malliris & Sabir Ghauri, UWE

Combinational Circuits

Binary values of outputs are a function of binary

combination of inputs

Outputs at any given time are entirely dependent

on inputs that are present at that time

3

Combinational

Circuitsn inputs m outputs

Adding 2 Numbers

Write the truth table for addition of 2 bits A & B

Write Boolean representation for Sum & Carry

S = A/B + AB/ = A B

C = AB

4

A B Sum (S) Carry (C)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Adding 2 Numbers (Cont.)

Draw logic circuit

This is called a half adder

5

Source: Wikipedia.org

Adding 2 Numbers & a Carry

Write the truth table for addition of 2 bits A & B

as well as a carry from previous low-order bit

6

A B Cin S Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Adding 2 Numbers & a Carry (Cont.)

Write Boolean representation for Sum & Carry

Hint – use k-maps

S = (A B) Cin

Cout = AB + (A B)Cin

7

ab

c

00

01

11

10

0 1

1

0

1

0

0

1

0

1

ab

c

00

01

11

10

0 1

0

1

1

1

0

0

1

0

S = Cout =

Adding 2 Numbers & a Carry (Cont.)

Draw logic circuit

This is called a full adder8

Source: www.setupsolution.com/how-to-design-a-half-adder-and-full-adder-in-verilog-at-gate-level-modeling/

Schematic Representation of Full

Adder

9

Source: http://en.wikibooks.org

(A B)

AB

n-bit Adder (Ripple Carry Adder)

10

Decoders

Suppose a simple microprocessor supports

following 2 instructions

ADD

LOAD

When these instructions execute they’ll need to

activate different circuits

Which circuit is determined by 2 most significant bits11

Decoders

Converts binary data from n coded inputs to a

maximum of 2n unique outputs

Called n-to-2n decoder

12

Decoder

b0

b1

Adder

Loader

d0

d1

d2

d3

Decoders

Truth table for a 2-to-4 decoder

13

b0 b1 d0 d1 d2 d3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

Decoders

Draw logic circuit of a 2-to-4 decoder

14

b0

b1d0

d1

d2

d3

Source: www.allaboutcircuits.com/vol_4/chpt_9/4.html

3-to-8 Decoder

15Source: www.edwardbosworth.com/CPSC2105/Lectures/Slides_05/Chapter_03/DecodersAndMux.htm

Decoder Expansion

Build a 3-to-8 decoder using 2-to-4 decoders

16

Source: http://dc167.4shared.com/doc/

or00nekd/preview.html Source: www.teachurselfece.com/2012/

02/decoders.html

Decoders (Cont.)

ADD

LOAD

Also helps us select which registers to use

17

18

Use of Decoders Inside CPU

A

E

D

C

B

ALU

Addre

ss B

us

Control Unit

IR

FLAG

ALU

PC

+1

Data

Bus

CT

RL B

us

Encoders

Reverse process of a decoder

4-to-2 encoder

3-to-8 encoder

19

Source: www.electronics-tutorials.ws/combination/comb_4.html

Encoders

Draw logic circuit of a 4-to-2 encoder

20

D0

D3

D1

D2

Q0

Q1

Priority Encoder

21

Source: www.electronics-tutorials.ws/combination/comb_4.html

22

Internal Structure

A

E

D

C

B

ALU

Addre

ss B

us

Control Unit

IR

FLAG

ALU

PC

+1

Data

Bus

CT

RL B

us

Internal Structure (Cont.)

23Source: www.transtutors.com/homework-help/computer-

science/computer-architecture/cpu/general-register-organization/

Multiplexer

Receives binary data from 2n lines & connect

them to a single output line based on a selection

By applying a control signals we can steer any

input to the output24

Multipl-

exer

d0

d1

s0 s1

qd2

d3

Multiplexer (Cont.)

Truth table

25

s0 s1 q

0 0 d0

0 1 d1

1 0 d2

1 1 d3

Multiplexer (Cont.)

Logic circuit

26

d0

d1

d2

d3

q

Source: www.ee.surrey.ac.uk/Projects/CAL/digital-logic/multiplexer/index.html

8-to-1 Multiplexer

27

Source: http://users.cis.fiu.edu/~prabakar/cda4101/Common/notes/lecture08.html

8-to-1 Multiplexer using 4-to-1 & 2-to-1

Multiplexers

28

Source: www.exploreroots.com/dc28.html

Demultiplexer

Reverse process of a multiplexer

By applying a control signals we can steer the

input signal to one of the output lines

29

Demult-

iplexer

q0

q1

s0 s1

dq2

q3

Demultiplexer (Cont.)

Truth table

Logic circuit

30

s0 s1 q0 q1 q2 q3

0 0 d

0 1 d

1 0 d

1 1 d

d

q0

q1

q2

q3

s0 s1Source: http://do-area.blogspot.com/p/multiplexer-demultiplexer.html

Demultiplexer Using Decoder

31Source: http://en.wikipedia.org

Multiplexer/Demultiplexer -

Application in Telecommunication

32Source: http://digilogwiki.com/index.php?title=Multiplexers/Demultiplexers

Summary

33Source: www.transtutors.com/homework-help/computer-

science/computer-architecture/cpu/general-register-organization/