Digital Phase Locked Loop

Design Phase Locked Loop Accuracy towards Femtosecond Magnitude

By

Wendi LIU, Hong X. QIAN, Jun S. HUANG, Qi CHEN

May 16-17, 2015, Dalian, Liaoning, China

2015 4th International Symposium on Electrical & Electronics Engineering

Power Matters. 2

About the authors

� The authors is around the world:

� Mr. Liu is a full time master student at UCLA, who pioneered the research in mathematical models for analog and digital circuits, he collaborates well with industry partners.

� Hong was among the key engineers who set up the first automation line in China for Purina (now part of Nestle), her major is automation and its applications, she is lead engineer of Wireless Mobi Solution.

� Prof. Huang is the distinguished professor at Jiangsu University, who has initiated a number of multi-national industry-academic collaborations, he is co-founder of GenieViewInc.

� Mr. Chen is among the top 10 students at Suqian College, Jiangsu University, who has co-invented a number of patents with Prof. Huang, and get involved in a number ofindustrial projects.

� The university campus at Suqian: • Xiang Yu (232 years BC - 202 BC) is a Chinese military thought Soldiers situation

representatives one of the strongest generals in Chinese history, because he had"feather brave, goes through the ages".

24th International Symposium on Electrical & Electronics Engineering

Power Matters. 3

Agenda

1. BACKGROUND

2. INTRODUCTION

3. MULTIPLE RATE PLL DESIGN

4. MATLAB SIMULATION

5. CONCLUSION AND FUTURE WORK

1.


Power Matters.

1. Background

� There is an increasing need for highly accurate stable clock sources,

� to drive modern digital positioning electronics equipment,

� especially in the telecommunications related sector, such as LTE-A,

� Release 11 for high speed train.

Power Matters. 5

2. Problem: remove both DCO/ VCO noises

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We have combined the advantages of four approaches in

references, coming up with our own unique structure: where two

phase/frequency detectors and one multiple rate digital filter are

used:

• similar to SiLabs digital loop, but employing multi-rate, instead

of the single rate;

• similar to Hittite’s high order filter, but done in the digital

domain;

• similar to TI’s double loop, but used only one loop, to drive

down the cost;

• similar to Mitsubishi’s homogeneous PFDs, but designed on

heterogeneous PFDs.


Power Matters.64th International Symposium on Electrical & Electronics Engineering

3.1 Overall Block Diagram

Where Kdet, KVCO, and Kloop are the gains of the PFD, VCO, and loop filter respectively


3.2 Controlling the Feedback Divider

1. Initialize the C/C++ code

2. Pick PLL mode integer Case 3.1 or else Case 3.2.

3. Case 3.1: Calculate DCO output frequency

Case 3.2: Calculate Fractional feedback division

4. Calculate the average multi-rate loop gain

5. Calculate the estimated output clock jitter

6. If it doesn’t meets IEEE1588 requirement go to step 2

7. Program the PLL, and adjust the Kalman filter

8. Check if the clock meet ITU-TG.8261 wander requirement

9. If yes, wait a fixed period, if no, go to step 7

10. Go back to step 8.


3.3 Two rate Digital loop filter


4. Matlab Simulink Model

Matlab Model:http://www.mathworks.com/matlabcentral/fileexchange/49854-multirate-dpll-model


4. Matlab Simulation Results

Number of PFDs

Filter Thermal

Noise

VCO noise

Reference noise

Other noise

Overall noise

One PFD 129fs 98fs 153fs 54fs 276fs

Two PFDs 81fs 59fs 71fs 29fs 91fsThe output spectrums with 2

PFDs (right) and 1 PFD (left)

Power Matters.

5. Conclusion and Future work

� We have discussed a phase locked loop frequency

synthesizer and its Matlab model comprising: a

multiple rate phase locked look.

� The simulation results and lab measurement show the

two-rate method is promising.

� The future work is to extend it to three or four rate

cases based on the latest quantum clock available

now.


Power Matters. 12

Thank you!

� Questions are welcome:

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[email protected]

4th International Symposium on Electrical & Electronics Engineering 4th International Symposium on Electrical & Electronics Engineering