Digital system design practical file

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Full details of the various practicals including circuit diagrams and truth tables.

Text of Digital system design practical file

  • 1 | P a g e INDEX S.NO DESCRIPTION PAGE 1. Write a program in VHDL to implement all logic gates using data flow modeling. 2 2. Write a program for the following circuits, check the waveform and the hardware generated using behavioral modeling: (a)Half Adder (b)Full Adder 16 3. Write a program for the 4:1 multiplexer, check the waveform and the hardware generated using behavioral modeling. 34 4. Write a program for the 1:4 demultiplexer, check the waveform and the hardware generated using behavioral modeling. 44 5. Write a program for the 8:3 encoder, check the waveform and the hardware generated using behavioral modeling. 54 6. Write a program for the 3:8 decoder, check the waveform and the hardware generated using behavioral modeling. 65 7. Write a program to implement 1-bit comparator in VHDL using behavioral modeling. 73 8. Write a program in VHDL to implement up-down counter using behavioral modeling. 80 9. Write a program to implement Binary to Gray code converter using behavioral modeling in VHDL 89 10. Write a program for the D flip-flop, check the waveform and the hardware generated using behavioral modeling. 95 SIGNATURE NO.
  • 2 | P a g e Program 1 Aim: Write a program in VHDL to implement all logic gates using data flow modeling. Apparatus: Tool used: Xilinx 8.2i PC specification: 1GB RAM, 320GB hard disk Theory: AND gate: The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is sometimes omitted i.e. AB. OR gate: The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high. A plus (+) is used to show the OR operation. NOT gate: The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is also known as an inverter. If the input variable is A, the inverted output is known as NOT A. This is also shown as A', or A with a bar over the top, as shown at the outputs. The diagrams below show two ways that the NAND logic gate can be configured to produce a NOT gate. It can also be done using NOR logic gates in the same way. NAND gate: This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on the output. The small circle represents inversion. NOR gate: This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on the output. The small circle represents inversion. XOR gate: The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its two inputs are high. An encircled plus sign ( ) is used to show the EOR operation. XNOR gate: The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low output if either, but not both, of its two inputs are high. The symbol is an EXOR gate with a small circle on the output. The small circle represents inversion.
  • 3 | P a g e VHDL code for implementing logic gates using data flow modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity gates_new is Port ( a : in STD_LOGIC; b : in STD_LOGIC; y1 : out STD_LOGIC; y2 : out STD_LOGIC; y3 : out STD_LOGIC; y4 : out STD_LOGIC; y5 : out STD_LOGIC; y6 : out STD_LOGIC; y7 : out STD_LOGIC); end gates_new; architecture Behavioral of gates_new is begin y1 y5, y6 => y6, y7 => y7 ); tb : PROCESS BEGIN -- Place stimulus here a carry ); tb : PROCESS BEGIN a sum, carry => carry ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish -- Place stimulus here a Y
  • 32 | P a g e ); tb : PROCESS BEGIN -- Place stimulus here i0 clr, d => d, q => q ); tb : PROCESS BEGIN -- Place stimulus here clk