HYDERABAD | VIJAYAWADA | GUNTUR

Accords IEEE & International Standards Mobile: 9603150547

Vision Solutions

Uppal, Hyderabad | 4/13 Brodipet, Guntur | Benz Circle, Vijayawada

E-Mail:visionsolutions.9@gmail.com, call-9603150547

Web site: www.visiongroups.org

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VLSI PROJECT LIST

1) AN INVENTIVE DESIGN OF 4*4 BIT REVERSIBLE NS GATE

2) DESIGN OF REVERSIBLE COUNTER

3) DESIGN AND IMPLEMENTATION OF 16-BIT RISC PROCESSOR

4) A LOW COST OFDM MODULATION SCHEMES FOR DATA COMMUNICATIO N

5)DESIGN AND IMPLEMENTATION OF LOW POWER DIGITAL FIR FILTER

BASED ON LOW POWER MULTIPLIERS AND ADDERS ON XILINX FPGA

6) DESIGN AND IMPLEMENTATION OF ZIGBEE TRANSMITTER USINGVERILOG

7)DESIGN AND IMPLEMENTATION OF 32 BIT UNSIGHNED MULTIPLIER USING

CLAA AND CSLA

8) DESIGN OF HIGH SPEED LOW POWER MULTIPLIER USING REVERSIBLE

LOGIC: A VEDIC MATHAMATICAL APPROACH

9) THE APPLICATION OF BUS CODING IN DESIGNING OF LOW POWER SOC

BASED O WISHBONE

10) OPTIMIZED REVERSIBLE VEDIC MULTIPLIERS FOR HIGH SPEED LOW

POWER OPERATIONS

11) AN FPGA BASED HIGH SPEED IEEE - 754 DOUBLE PRECISION FLOATING

POINT ADDER/SUBTRACTOR AND MULTIPLIER USING VERILOG

12) DESIGN AND IMPLEMENTATION OF 8-BIT VEDIC MULTIPLIER

13) LOW POWER AND AREA-EFFICIENT CARRY SELECT ADDER

14) RTL DESIGN AND VLSI IMPLEMENTATION OF AN EFFICIENT

CONVOLUTIONAL ENCODER AND ADAPTIVE VITERBI DECODER

15) DESIGN OF HIGH PERFORMANCE 64 BIT MAC UNIT

HYDERABAD | VIJAYAWADA | GUNTUR

Accords IEEE & International Standards Mobile: 9603150547

Vision Solutions

Uppal, Hyderabad | 4/13 Brodipet, Guntur | Benz Circle, Vijayawada

E-Mail:visionsolutions.9@gmail.com, call-9603150547

Web site: www.visiongroups.org

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16) AGING-AWARE RELIABLE MULTIPLIER DESIGN WITH ADAPTIVE HOLD

LOGIC

17) DESIGN OF DIGIT-SERIAL FIR FILTERS: ALGORITHMS, ARCHITECTURES,

AND A CAD TOOL

18) LOW-COST FIR FILTER DESIGNS BASED ON FAITHFULLY ROUNDED

TRUNCATED MULTIPLE CONSTANT MULTIPLICATION/ACCUMULATION

19) DESIGN OF REED-MULLER ENCODER FOR MULTIPLE ERROR DETECTION

20)CYCLIC REDUNDANCY CHECK GENERATION USING MULTIPLE LOOKUP

TABLE ALGORITHMS

21) ARITHMETIC & LOGIC UNIT (ALU) DESIGN USING REVERSIBLE CONTROL

UNIT

22) AN EFFICIENT MULTIPLICATION ALGORITHM USING NIKHILAM METHOD

23) TEST PATTERN GENERATOR USING LFSR FOR BIST

24) OPTIMIZED SHIFT REGISTER DESIGN USING REVERSIBLE LOGIC

25) AN EFFICIENT IMPLEMENTATION OF FLOATING POINT MULTIPLIER

26) A NEW REVERSIBLE DESIGN OF BCD ADDER

27) ARITHMETIC & LOGIC UNIT (ALU) DESIGN USING REVERSIBLE CONTROL

UNIT

28) DESIGN AND CHARACTERIZATION OF PARALLEL PREFIX ADDERS USING

FPGAS

29)IMPLEMENTATION OF WIFI MAC TRANSMITTER BY VHDL MODELLING

30)REDUCING THE COMPUTATION TIME IN (SHORT BIT-WIDTH) TWO'S

COMPLEMENT MULTIPLIERS