IEEE VLSI ECE PROJECT LIST

HYDERABAD | VIJAYAWADA | GUNTUR

Accords IEEE & International Standards Mobile: 9603150547

Vision Solutions

Uppal, Hyderabad | 4/13 Brodipet, Guntur | Benz Circle, Vijayawada

E-Mail:[email protected], call-9603150547

Web site: www.visiongroups.org

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VLSI PROJECT LIST

1 )A New Structure of Low-Power and Low-Voltage Double-Edge Triggered Flip-Flop(ieee

2014)

Abstract:

In this paper a novel low-power double-edgetriggered flip-flop is introduced. Double-edge

triggeredFlip-Flops have the data signal changes on both the clockedges. Thus, low swing clock

results in lower powerconsumption and the data throughout are preserved. Today, the leakage

current has become a critical featurefor integrated circuit (IC) designers because it leads to more

power consumption. So in this paper some methodshave been presented to control the leakage

current. Theproposed circuit is simulated in 0.35 μm CMOStechnology with the power supply of

1.5V. Thesimulations are carried out by applying SPICEsoftware. The results of the proposed

circuit show 180nWpower dissipation. The number of clock transistorsdecrease which in turn

results in lower leakage current,hence the power consumption reduces.

2) Design ofHigh Performance 64 bit MAC Unit (IEEE 2013)

Abstract –

A design of high performance 64 bitMultiplier-and-Accumulator (MAC) is implemented in

this paper. MAC unit performs important operation inmany of the digital signal processing

(DSP)applications. The multiplier is designed using modifiedWallace multiplier and the adder is

done with carrysave adder. The total design is coded with verilog-HDLand the synthesis is done

using Cadence RTL complierusing typical libraries of TSMC O.18um technology.

The total MAC unit operates at 217 MHz. The totalpower dissipation is 177.732 mW.



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3) Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA(IEEE

2013)

Ahstract-

This project deals with the comparison of the VLSIdesign of the carry look-ahead adder (CLAA)

based 32-bitunsigned integer multiplier and the VLSI design of the carryselect adder (CSLA)

based 32-bit unsigned integer multiplier.Both the VLSI design of multiplier mUltiplies two 32-

bitunsigned integer values and gives a product term of 64-bitvalues. The CLAA based multiplier

uses the delay time of 99ns for performing multiplication operation where as in CSLA

based multiplier also uses nearly the same delay time formultiplication operation. But the area

needed for CLAAmultiplier is reduced to 31 % by the CSLA based multiplier tocomplete the

multiplication operation. These multipliers areimplemented using Altera Quartus II and timing

diagrams areviewed through avan waves.

4)Optimized Reversible Vedic Multipliers for High Speed Low Power Operations(IEEE

2013)

Abstract— Multiplier design is always a challenging task; how many ever novel designs

are proposed, the user needs demands much more optimized ones. Vedic mathematics is world

renowned for its algorithms that yield quicker results, be it for mental calculations or

hardware design. Power dissipation is drastically reduced by the use of Reversible logic. The

reversible Urdhva Tiryakbhayam Vedic multiplier is one such multiplier which is effective

both in terms of speed and power. In this paper we aim to enhance the performance of the

previous design. The Total Reversible Logic Implementation Cost (TRLIC) is used as an aid

to evaluate the proposed design. This multiplier can be efficiently adopted in designing Fast

Fourier Transforms (FFTs) Filters and other applications of DSP like imaging, software

defined radios, wireless communications.



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5)Design of Digit-Serial FIR Filters: Algorithms,Architectures, and a CAD Tool(IEEE

2013)

Abstract—In the last two decades, many efficient algorithms and architectures have been

introduced for the design of lowcomplexity bit-parallel multiple constant multiplications (MCM)

operation which dominates the complexity of many digital signal processing systems. On the

other hand, little attention has been given to the digit-serial MCM design that offers alternative

lowcomplexity MCM operations albeit at the cost of an increased delay. In this paper, we

address the problem of optimizing the gate-level area in digit-serial MCM designs and introduce

highlevel synthesis algorithms, design architectures, and a computeraided design tool.

Experimental results show the efficiency of the proposed optimization algorithms and of the

digit-serial MCM architectures in the design of digit-serial MCM operations and finite impulse

response filters.

6)Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant

Multiplication/Accumulation

Abstract—Low-cost finite impulse response (FIR) designs are presented using the concept of

faithfully rounded truncated multipliers. We jointly consider the optimization of bit width

andhardware resources without sacrificing the frequency response and output signal precision.

Nonuniform coefficient quantization with proper filter order is proposed to minimize total area

cost. Multiple constant multiplication/accumulation in a direct FIR structure is implemented

using an improved version of truncated multipliers. Comparisons with previous FIR design

approaches show that the proposed designs achieve the best area and power

results.

7) Boostable Repeater Design for Variation Resilience in VLSI Interconnects

Abstract—Process variations and circuit aging continue to be one of the main challenges to the

power-efficiency of VLSI circuits, as a considerable power budget must be allocated to cushion



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timing variations. A design-time allocation implies uniform power consumption on all fabricated

instances, even if many instances do not have strong variations. Adaptive design provides a

power-efficient approach to variation tolerance, since it uses power only when the variations of a

circuit instance are harmful. This paper is an effort toward supply voltage adaptation for

variation resilience in VLSI interconnects. The main idea is a boostable repeater design that can

transiently and autonomously raise its internal voltage rail to boost switching speed. The

boosting can be turned on/off to compensate variations. The boostable repeater design achieves

fine-grained voltage adaptation without stand-alone voltage regulators or an additional power

grid. Since interconnect is a widely recognized cause of bottleneck in chip performance, and

tremendous repeaters are employed on chip designs, boostable repeater has plenty of chances to

improve system robustness. Experimental results indicate that our approach significantly

outperforms existing techniques, including over-design, conventional adaptive supply

voltage system, and online adjustable buffer.

8)An Inventive Design Of 4*4 Bit Reversible NS Gate(IEEE 014)

The model of computing in which the computational progression is reversible or to some extent

time inverting is entitled reversible computing. In the modern epoch reversible logic has

materialized as a promising, competent technology com prising its applications in low power

CMOS, quantum computing, nanotechnology, and optical computing. The conventional gates

such as AND, OR, and EXOR are not reversible. Here in this manuscript we put forward a 4*4

reversible gate design called "NSG". The most noteworthy, considerable attribute of the

proposed gate is that it can work individually as a reversible full adder, reversible full subtractor,

reversible half adder, and reversible half subtractor. That is now we are capable of implementing

reversible full adder, subtractor and reversible half adder, subtractor with a single gate only. The

proposition of this meticulous

9) Aging-Aware Reliable Multiplier Design WithAdaptive Hold Logic(IEEE 2014)

Abstract—Digital multipliers are among the most critical arithmetic functional units. The overall

performance of these systems depends on the throughput of the multiplier. Meanwhile, the

negative bias temperature instability effect occurs when a pMOS transistor is under negative bias



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(Vgs = −Vdd), increasing the threshold voltage of the pMOS transistor, and reducing multiplier

speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS

transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the

system may fail due to timing violations. Therefore, it is important to design reliable high-

performance multipliers. In this paper, we propose an aging-aware multiplier design with a novel

adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through

the variable latency and can adjust the AHL circuit to mitigate performance degradation that is

due to the aging effect. Moreover, the proposed architecture can be applied to a column- or row-

bypassing multiplier. The experimental results show that our proposed architecture with 16 ×16

and 32 ×32 column-bypassing multipliers can attain up to 62.88% and 76.28% performance

improvement, respectively, compared with 16×16 and 32×32 fixed-latency column-bypassing

multipliers. Furthermore, our proposed architecture with 16 × 16 and 32 × 32 row-bypassing

multipliers can achieve up to 80.17% and 69.40% performance improvement as compared with

16×16and 32 × 32 fixed-latency row-bypassing multipliers.

Engineering

IEEE VLSI ECE PROJECT LIST