De lay Mode l s A n d Mode l ing S ty lesO f

VHDL

PowerPoint Presentationon

Teacher Assessment Exam-II

Subject:Digital System Design

Submitted By: Ashish Pandey Guided By: A. P. Dongre2nd Yr | 4th SEM | Roll No. 30 (C),E T&C Engineering,G.H.R.C.E.

Ass. Professor,ET&C Department,G.H.R.C.E.

Electronics and Tele Communication Engineering Department

Delay Models in VHDL

VHDL Delay Models

• Delay is created by scheduling a signal assignment for a future time.

• Delay in a VHDL cycle can be of several types

• Inertial

• Transport

• Delta

Inertial Delay

•It is a Default delay type in VHDL.•It is default because it behaves similar to actual device.•It is most commonly used today, because in most cases, it is accurate for the designers needs.•In Inertial Delay, the output signal of the device has inertia which must overcomes for the signal to change values.

Transport Delay

•Transport Delay is not a default in VHDL.•It must be specified by users.•It represent wire delay in which pulse, no matter how small, is propogated to the output signal delayed by delay value specified.•It is use for wire delay on PC board, and path delay on ASIC.

Delta Delay

• Delta delay needed to provide support for concurrent operations with zero delay

– The order of execution for components with zero delay is not clear

• Scheduling of zero delay devices requires the delta delay

– A delta delay is necessary if no other delay is specified– A delta delay does not advance simulator time– One delta delay is an infinitesimal amount of time– The delta is a scheduling device to ensure repeatability

Modeling Styles in VHDL

Modeling Styles

• There are three modeling styles:

• Behavioral (Sequential)

• Data flow

• Structural

Sequential / Behavioral Style

• In behavioural model, one needs to code the behaviour of the system to be designed. If we consider c < = a and b, the behaviour is that, the output should be one (1) whenever both the inputs are one (1). 

• we can code it like this: if (a=1 and b=1) then c<='1'; else c<='0'; 

• Or, we can even have the behavior like this: case s is when "00"=>c<='0'; when "01"=>c<='0'; when "10"=>c<='0'; when "11"=>c<='1'; 

• We are implementing the LOGIC here. We are least bothered about the circuits that can implement this logic. Hence, it is a system level or logic level modeling style. 

Advantages & Disadvantages

Data flow Style

• In this model, the input data simply flows into the output. That is, we will be implementing the relation between input and output terminals directly. 

• For example, c < = a and b; 

• Here, the output c is an ANDing of a and b. We are actually implementing the direct relation between inputs and outputs. That is, c = a + b. 

• Hence, we need not write any complex conditional statements here in data flow model. 

• Simply implement the output expression.• Here, we are implementing the code at a very basic

level i. e. circuit level or gate level. 

Advantages & Disadvantages

Structural Style

• In structural modeling of VHDL, the concept of components is used. In this model, the system to be designed is considered as a combination of sub structures. These sub structures are called components. 

• For example, a full adder is a combination of two half adders and an or gate.

• Hence, the components used for designing a full adder are  half adder & OR gate.

Advantages & Disadvantages

Thank You