MUDIT KAPOOR 201 S 4th Street, Colonnade Apartments, APT 735, San Jose, CA, 95112, USA +1 (408) 650-2159 / kapoor.mudit@hotmail.com http://www.linkedin.com/pub/mudit-kapoor/38/363/b29/ Electrical Engineering Graduate student at San Jose State University specializing in Digital IC Design with 3 years of experience in Board System Design seeking Internship/ Full time opportunity. EDUCATION Master of Science (M.S), Electrical Engineering, SAN JOSE STATE UNIVERSITY (U.S.A) GPA 3.8/4.0 (Aug 2014 - Expected May 2016)

Completed Coursework: Linear System Theory, Advanced Digital System Design and Synthesis, Principles of Semiconductor Devices, ASIC CMOS Design, CMOS digital IC circuits (Physical Design), Advanced Computer Architecture, SOC Design and Verification.

Bachelor of Engineering (B.E), Electronics and Communication, KURUKSHETRA UNIVERSITY (INDIA) (Aug 2007 - July 2011) GPA 3.76/4.0 TECHNICAL SKILLS • Simulation/Design Entry Tools: Cadence Allegro, Cadence Allegro PCB Librarian, Cadence PCB SI, Cadence orCAD Capture/CIS,

Cadence Virtuoso, Concept HDL, LTSpice, Intel VR validation, TI Fusion power Designer, Lattice ispVM, Lattice PAC Designer Synopsys, VCS, LabVIEW.

• Languages: Verilog, Perl, Unix, System Verilog.

WORK EXPERIENCE Organization: Analog Devices Inc., San Jose, California, USA (June 2015 – Dec 2015) Designation: Test Engineering Intern • Testing various Analog Devices for Power on functionality and reliability using LabVIEW. • Designing, Developing and debugging of Automatic Test Equipment (ATE) and its use in testing various electronic devices. • Written Script in Perl to Parse Adice waveform viewer (.plt) file to synopsys (.vcd) tool Compatible.

Organization: Wipro Technologies, Bangalore, India (Oct 2011 – Jul 2014) Designation: Hardware Design Engineer • Electronic Circuit/Interface design, Schematic’s, PCB Stack-up creation, PCB Layout (guidance). • Use of High End Oscilloscopes, Design of Low power DC-DC generation and distribution, I2C, SPI. • Board bring-up, Testing, Functional verification, Reliability, Thermal, EMI/EMC compliance.

San Jose State University: Teaching Assistant EE271: Advanced Digital System Design and Synthesis : Assisting students on Verilog projects, Assignments. CMPE110: Electronics for Embedded Systems: Duties- Assisted students on use of oscilloscope, active and passive circuit design and analysis, Lab report grading. CMPE240: Advanced Computer Design: Duties-Assisted Students on Verilog coding, project viva, Report grading.

ACADEMIC PROJECTS

The Implementation of AHB based DDR SDRAM Memory Controller Softcore (Sept 2015 – May 2016) Design and Synthesis of AHB bus based interface of DDR SDRAM Memory using Verilog Language. UART design: (Sept 2015) Design and Synthesis of UART protocol using 250nm Toshiba Library at RTL Level. RMS calculator (Feb 2015 - May 2015)

Design and Synthesis a push-pull interface based Root Mean Square Calculator (RMS) for a series of 32-bit Signed integers using Pipelined Division and Square root algorithm at 250MHz clock on 250nm technology at RTL level.

4-Bit up/down synchronous counter with asynchronous reset (Feb 2015 - May 2015) Designed schematic and physical layout using 45nm technology with corner analysis, clean DRC/LVS on Cadence Virtuoso.

8-Bit simple Scalar Micro-processor (Aug 2014 - Dec 2014) Design and synthesis 8-bit scalar processor using 250nm technology at RTL level featuring an interface with 256 bytes of external memory.

INDUSTRY PROJECTS 3U Rack High Performance Computing Server Design using Intel Ivy Bridge processor (April 2012 - July 2014)

Project Abstract: The Server is based on the Intel’s 64 bit, IVY Bridge-EX family of Xeon processor. Each Board is a Dual CPU configuration but can communicate among 16 CPUs through Extended-QPI link. Memory has hot swappable feature. The design include DDR3/4, PCIe Gen3, SATA interfacing, Ultra Capacitive Module. It was an end-to-end design. Activities Undertaken: Feasibility study, Design of Low voltage DC-DC power Generation and Distribution, I2C, IR Drop Analysis, Timing Analysis, Pre/Post layout guidance, FPGA coding, Lattice Power Manager’s, Design bring-up and Debugging in Assembly House - China, Electronic Load Testing, Four Corner testing, component selection, release notes.

Graphic Process Unit for HPC Blade Server using Intel’s Sandy Bridge processor (Jan 2012- April 2012) Project Abstract: Design of Graphic Process Unit based on NVIDIA Graphics card and Intel’s Sandy-Bridge processor. Activities Undertaken: Duties include Component Selection, Schematic entry, BOM preparation, Net list Generation, component library handling, Gerber release.