San Jose, CA 95112 Phone: +1 (979) 267-9832 RA H U L GA L A

z.rahulgala@gmail.com http://rahulgala.com

SKILLS Languages: Verilog, SystemVerilog, Python, C++, Perl, TCL, HTML. | Methodology: UVM methodology. Software Tools: Synopsys VCS, GTK Wave, Design Vision, Vim, Proteus, Xilinx ISE, Multisim, Quartus Prime II. Bus Protocols: AMBA, APB, AXI 4.0, AXI4-Lite, AHB, PCI, PCIe, SPI, I2C, UART.

Proficiency: RTL Design, Static Timing Analysis, Test and Debug, Digital Logic Design, Timing Closure, DFT.

Other: ASIC and SoC design, Simulation & Verification of Design, Synthesis and Constraint development, SVA.

EMPLOYMENT

Embedded Hardware Intern System Electronics & Optronics Pvt. Ltd. (Nov’10-Mar ‘11) • Designed & tested more than 30 printed circuit boards (PCB) for control panel of offset/webpage printing machines.

• In circuit/off ckt testing of Integrated circuits and other ckt of various control panel & performed RPR problem diagnosis.

• Optimizing existing functional analog circuit to upgrade various offset printing machines with PLC and HMI.

Co-Founder and Product Designer Z Series Innovations Pvt. Ltd. (Feb’13 – Dec’14) • Start-up in e-learning & project development with team of 25 members catering to about 80,000 monthly online visitors.

• Published 300+ online tutorial pages on varied field of Electronics (VLSI, Embedded System, etc.)

Award: Top 25 Start-up companies across India at Tata First DOT Conference 2014 while in undergrad (www.zseries.in)

Tech Evangelist Lions Club International (Oct’11 – Oct’12) • A year’s volunteer services at various technical events including robotics & embedded systems workshops for enthusiast.

EDUCATION M.S. in Electrical & Electronics San Jose State University Anticipated in May 2017

• M.S. in Electrical Engineering, specializing in VLSI- ASIC/VLSI Circuits, Digital Logic System Design & Verification.

• Coursework: ASIC CMOS design, Digital design & synthesis, SoC design & verification, Advance comp. architectures.

B.E. and Diploma (Electronics) Shah & Anchor Kutchhi Engineering College GPA: 3.5/4.0

• B.E. in Electronics Engineering, Specializing in Embedded Systems and Digital Logic Design May 2014 • Coursework: Computer Architecture & Organization, Linear Integrated Circuits & Design, Electronics Product Design.

TECHNICAL EXPERIENCE System Model Design of AXI Bridge using SystemVerilog & its functional verification using UVM (Aug’16-May’17)

• System model design of an AXI4-Lite to AXI4-Lite bridge using SystemVerilog and verifying using UVM methodology

for multi master-multi slave (low-throughput memory-mapped communication) environment.

• Traffic performance, request and response latency generation, multi reset functionality, arbitration check and full

bandwidth check are focused for verification. Developed Python script to generate verification template & parse reports.

Design of a Network-On-Chip along with NXP cyclic redundancy check(CRC) using SystemVerilog(Aug’16-Dec’16)

• Agile Design of NOC as bus-master functioning on packet size of 9-bit with master-slave communication and performing

CRC error detection. Implemented CRC module from NXP MKW2xD Reference Manual and designed an Arbiter.

• A high-speed communication at 100MHz for different burst size with increase in efficiency achieved.

Design of Altera NIOS-II subset Instruction set Architecture & implemented 3 varied applications (Jul’16-Aug’16)

• A five-staged pipelined NIOS-II architecture designed using Verilog & results analyzed using GTKWave wave viewer.

• Applications like Sum of Array, Dot Product and Factorial program were executed successfully on this architecture.

Design of Box Muller transform using double precision IEEE floating point adder multiplier (Jan’16-May-16)

• RTL design of 64-bit Floating point adder-multiplier using Toshiba tc240c library- 250nm technology

• A pipelined architecture of two flag model FIFO memory embedded to build a Box Muller Transform ckt using Verilog.

• Simulations & Gate Level synthesis performed by Synopsys VCS & GTKWave. Synthesis Script in TCL.

• 8 bit of precision in result with result pushed out every clock cycle at 220 MHz achieved. Inserted SCAN methodology

for testing. Developed Python script to extract synthesis reports for analysis.

Publications, Honors and Patents Accomplished paper on “Hardware issues in computer architecture and ways to mitigate them” (Aug’16-Dec-16)

• A research paper that illustrate the structural hardware issues in pipelined stages of CPU and data losses occurred in

memories (ex. Row hammering) with their proposed methodology/solutions to improvise the performance and efficiency.

Patent: Applied for Multi-Dimensional Robot Kit (Application no. 3196/MUM/2013) (research in progress) • An SoC kit to learn, program and build variety of robots for educational and research purpose.

• A low-cost advance multi-dimensional structural modular kit with plug-code-play feature with custom processor design.