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- Designed a standard cells with gates including Inverter, two input NAND, two Input NOR, two Input XOR, 2:1 Multiplexer, AOI22, OAI3222 and D Flip Flop with minimum area & diffusion breaks by using IBM130 nm process technology. - Involved library characterization using NCX, RTL synthesis of VHDL code of 32 bit ALU Chip design using Synopsys Design Vision.
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Cell Library Project #4
The University of Texas at Dallas
Department of Electrical Engineering
EECT 6325 VLSI Design
Project #4
“CELL LIBRARY DESIGN”
Team Members:
1) Bharat Biyani (2021152193)
2) Gaurav Kasar (2021177056)
3) Zarin Tasnim Pulam (2021186931)
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INDEX
Sr.No Description Page
1 INVERTER 3-6
2 NAND2 7-10
3 NOR2 11-14
4 XOR2 15-18
5 AOI22 19-22
6 OAI3222 23-26
7 MUX 2:1 27-30
8 D – Flip Flop 31-45
9 LINED UP CELL 46
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1) Inverter (out = !in)
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Layout (Full view)
Inverter Layout upper view
Inverter Layout middle view
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Inverter Layout Lower view
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Schematic of Inverter
Inverter simulation waveform
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2) NAND2 [out = !(a&b)]
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Layout (Full view)
NAND2 Layout upper view8
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NAND2 Layout middle view
NAND2 Layout Lower view 9
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Schematic of NAND2
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NAND2 Simulation waveform
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3) NOR2 [out=!(a+b)]
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Layout (Full view)
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NOR2 Layout upper view
NOR2 Layout middle view
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NOR2 Layout Lower view
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Schematic of NOR2
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NOR2 Simulation waveform
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4) XOR2 [out= (((!a)&b)+((!b)&a))]
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Layout (Full view)
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XOR2 Layout upper view
XOR2 Layout middle view
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XOR2 Layout Lower view
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Schematic of XOR2
XOR2 Simulation waveform
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5) AOI22 [out=!((a&b)+(c&d))]
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Layout (Full view)
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AOI22 Layout upper view
AOI22 Layout middle view
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AOI22 Layout Lower view
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Schematic of AOI22
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AOI22 Simulation waveform
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6) OAI3222 [out= !((a+b+c)& (d+e) & (f+g) & (h+i))]
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Layout (Full view)
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OAI3222 Layout upper view
OAI3222 Layout middle view
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OAI3222 Layout Lower view
Schematic of OAI3222
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OAI3222 Simulation waveform
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7) MUX 2:1 [out= (((!s)&a)+(s&b))]
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Layout (Full view)
MUX 2:1 Layout upper view
MUX 2:1 Layout middle view
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MUX 2:1 Layout Lower view
Schematic of MUX 2:1
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MUX 2:1 Simulation waveform
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6) D – FLIP FLOP
Logic diagram of D- Flip Flop
The above figure shows the gate level diagram of the D flip-flop. The flip-flop uses two D-latches connected back to back (thus making the flip-flop circuit totally opaque for the whole of the clock period).The output is a complemented value of Q and hence we use an inverter at the end to get the desired output (Q). ‘Clock’ represents the clock signal. It is like a global clock signal that generates ‘∅’ and ‘∅ 'signals for the Tristate inverters.In the D-flip flop the Clock input (clock) to the Tri state inverter is given by inverting the input clock twice using two inverters. The clock output would be driving plenty of flip-flops; therefore in order to reduce the loading on a single node, two inverters have been connected back to back. This would increase the total area covered by the flip-flop but would also decrease the clock skew and hence latency in the design.Our report is for design and characterization of a falling-edge triggered master-slave D Flip-Flop with asynchronous reset. All transistors in our design contain four contacts in n-diffusion and six contacts in p-diffusion.
6.1 Layout generation concept
We have drawn our circuit diagram from the above gate level D-flip flop diagram and found the Euler trail to draw the Layout. Euler paths for PMOS and NMOS: 1st trail clock – clock2nd trail ∅ – D – ∅ – ∅ – out2 – out1 - Reset 3rd trail Reset – out4 – ∅ – ∅ - out2 – out3Note: Above values are with respect to gate of every transistor.These trail can be viewed in the below schematic diagram of the D Flip-Flop. There are 3 Eulertrails and 2 diffusion breaks in the schematic and layout.
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Schematic diagram of D Flip-flop
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6.2 Layout D flip-flop with Rulers:
We have used only two M2 layers. The height and width of the cell are 8.00 µm and 9.60µm respectively and the area is 76.8 µm2. After placing 6 contacts in P-diff and 4 contacts in N-diff, the width of P-diff comes to 2.28 µm and N-diff to 1.48 µm.
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Top Section of D Flip Flop:
Center section of D Flip Flop:
It can be clearly observed that the pins are placed such that there is uniform spacing an integer multiple of the grid spacing (0.48*n, where n= 1,2,3... for 120 nm technology)
Bottom Section of D Flip Flop:
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6.3 Waveform (Functionality of D Flip-Flop
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6.4 Characterization of D Flip Flop
Drop-dead setup time (Tsu_dd):
Drop dead setup time (Tsu_dd) is defined as the absolute minimum time required for the ‘D’ input signal to arrive before active clock edge (for our case its negative edge) so that the input signal can be captured correctly at the output. It is different for passing ‘0’ and passing ‘1’.
Optimum setup time (Tsu_opt):
Tdelay is given by Tsu+TClk->Q. The set up time for which Tdelay is minimum is called optimum setup time. It is different for passing ‘0’ and passing ‘1’.
Thold:
The time for which the data has to be held constant in order to be processed at the falling edge is called hold time. Data arriving after drop-dead setup time will not be propagated through the flip-flop, hence we can conclude that
Tsu_dd(1) = Thold(0) and Tsu_dd(0) = Thold(1).
Tclk->Q:
It is the time required for the output to have a stable/valid value after the falling edge of the clock.
The setup time (Tsu) and the Tclk -> Q can be calculated by simulating the D flip-flop functionality using the hspice files provided in the later section. The T su is calculated as the time delay between 50% of the input D to 50 % of the clock signal. The Tclk-
> Q can be calculated as the time delay between 50 % of the clock and 50 % of the output.
Now, Tdelay (Tsu+Tclk->Q) versus Tsu is plotted to get the minimum delay (optimum delay) for passing a 0 and 1.
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Characterization calculation
Setup ‘0’
In order to calculate setup time for 0:
Initially, make sure that the output is at logic 1. Give ‘0’ at the input D at different times with respect to the clock (prior and
after the sampling event of the clock), to see the how the output Q changes for each case.
The minimum time for which the output changes to a ‘0’ is considered the drop dead setup time for ‘0’. Before this time, the output cannot go to ‘0’(i.e., remains what it was previously).
Hence, the total time taken to setup a ‘0’ will almost be the same as the hold time of a ‘1’.
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Graph of Tsu(0) Vs Tdelay(0)
Table showing drop dead setup time (Tsu_dd) and the optimum setup time (Tsu_opt)
Time Tsu (0) TClk->Q(0) Tdelay(0) Comments
Tsetup(optimal) : Tsu_opt
26ps 170ps 196ps Optimum setup values for setup ‘0’
Tsetup(drop dead) : Tsu_dd
8ps 289ps 287ps This corresponds to Thold(1) ≈
Tsu_dd(0)
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Setup ‘1’:
In order to calculate setup time for 1 -
Initially, make sure that the output is at logic 0.
Give ‘1’ at the input D at different times with respect to the clock (prior and after the sampling event of the clock), to see the how the output Q changes for each case.
The minimum time for which the output changes to a ‘1’ is considered the drop dead setup time for ‘1’. Before this time, the output cannot go to ‘1’(i.e., remains what it was previously).
Hence, the total time taken to setup a ‘1’ will almost be the same as the hold time of a ‘0’.
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Graph of Tsu(1) Vs Tdelay(1)
Time Tsu(1) TClk->Q(1) Tdelay(1) Comments
Tsetup(optimal) : Tsu_opt(1)
41ps 169ps 210ps Optimum setup values for setup ‘1’
Tsetup(drop dead): Tsu_dd(1)
18ps 297ps 315ps This corresponds to Thold(0) ≈
Tsu_dd(1)
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6.5 Summary of D flip-flop
Dimensions of the cell:
Height of D Flip Flop= 8.00um
Width of D Flip Flop= 9.60um
Area of D Flip Flop= 76.8um2
Number of Vertical M2 used in Layout = 2 (excluding pin connections)
Number of Diffusions break in Layout = 2
Summary of D Flip-Flop times:
Time Tsu TClk->Q Tdelay Thold
Setting up 0 (optimal): Tsu_opt(0)
26ps 170ps 196ps
Setting up 0 (drop dead):
Tsu_dd(0)
8ps 289ps 287ps ≈18ps (Thold(1))
Setting up1 (optimal): Tsu_opt(1)
41ps 169ps 210ps
Setting up1 (drop dead):
Tsu_dd(1)
18ps 297ps 315ps ≈8ps (Thold(0))
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6.6 Hspice file
Checking the functionility of D Flip flop-
$ Hspice Code for DFF for checking the correct functionility -$ including the library.include "/home/cad/kits/IBM_CMRF8SF-LM013/IBM_PDK/cmrf8sf/V1.2.0.0LM/HSPICE/models/model013.lib_inc"
$ Spice netlist from extraction.include dfflvs.sp
$ Defining global variables.Global vdd! gnd!
$ for increasing the accuracy.option post runlvl=5
$ calling system to stimulatexi clock d reset q dff
$ assigning power supply value given as 1.2vvdd vdd! gnd! 1.2v
$ input voltage sourceVin1 reset gnd! PWL(0ns 0v 6500ps 0v 6593.75ps 1.2v)Vin2 clock gnd! pulse(0v 1.2v 0ns 93.75ps 93.75ps 1406.25ps 3000ps)Vin3 d gnd! pulse(0v 1.2v 0ns 93.75ps 93.75ps 1000ps 2000ps)cout out gnd! 25f
$ simulation step and simulation time.trans 1ps 12ns
$ measure steup time (tsu[0]), clock to output time(tclktoq) and delay time.measure tsu trig v(d) val=0.6 fall=1 targ v(clock) val=0.6v fall=2.measure tclktoq trig v(clock) val=0.6 fall=2 targ v(q) val=0.6 fall=1
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.measure tran td param='tsu + tclktoq
.end
Checking the functionility to pass ‘0’-
$ Hspice Code for DFF for passing '0'$ including the library.include "/home/cad/kits/IBM_CMRF8SF-LM013/IBM_PDK/cmrf8sf/V1.2.0.0LM/HSPICE/models/model013.lib_inc"
$ Spice netlist from extraction.include dfflvs.sp
$ Defining global variables.Global vdd! gnd!
$ for increasing the accuracy.option post runlvl=5
$ calling system to stimulatexi clock d reset q dff
$ assigning power supply value given as 1.2vvdd vdd! gnd! 1.2v
$ input voltage sourceVin1 reset gnd! 0v Vin2 clock gnd! pulse(0v 1.2v 0ns 93.75ps 93.75ps 1406.25ps 3000ps)Vin3 d gnd! PWL(0ns 1.2v t 1.2v 't+93.75ps' 0v)cout out gnd! 25f
$ simulation step and simulation time.tran 0.001ns 10ns sweep t 3000ps 5000ps 1ps
$ measure steup time (tsu), clock to output time(tclktoq) and delay time.measure tsu trig v(d) val=0.6 fall=1 targ v(clock) val=0.6v fall=2.measure tclktoq trig v(clock) val=0.6 fall=2 targ v(q) val=0.6 fall=1
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.measure tran td param='tsu + tclktoq'
.end
Checking the functionility to pass ‘1’-
$ Hspice Code for DFF for passing '1'$ including the library.include "/home/cad/kits/IBM_CMRF8SF-LM013/IBM_PDK/cmrf8sf/V1.2.0.0LM/HSPICE/models/model013.lib_inc"
$ Spice netlist from extraction.include dfflvs.sp
$ Defining global variables.Global vdd! gnd!
$ for increasing the accuracy.option post runlvl=5
$ calling system to stimulatexi clock d reset q dff
$ assigning power supply value given as 1.2vvdd vdd! gnd! 1.2v
$ input voltage sourceVin1 reset gnd! 0v Vin2 clock gnd! pulse(0v 1.2v 0ns 93.75ps 93.75ps 1406.25ps 3000ps)Vin3 d gnd! PWL(0ns 0v t 0v 't+0.09375ns' 1.2v)cout out gnd! 25f
$ simulation step and simulation time.tran 0.001ns 10ns sweep t 3000ps 5000ps 1ps
$ measure steup time (tsu[1]), clock to output time(tclktoq) and delay time50
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.measure tsu trig v(d) val=0.6 rise=1 targ v(clock) val=0.6v fall=2
.measure tclktoq trig v(clock) val=0.6 fall=2 targ v(q) val=0.6 rise=1
.measure tran td param='tsu + tclktoq'
.end
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Layout of Lined up cells
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