Traffic light Controller Design

University of Mauritius

Faculty of Engineering

Department of Electrical and Electronic Engineering

Programme: BEng(Hons) Electrical and electronic Engineering

(Year 3)

Module: Electronic System Design

TRAFFIC LIGHT CONTROLLER DESIGN

IVAN TIM OLOYA:0900153

KAVI GOPAUL:0913166

WILLIAM ULRICH JOUBERT:0900145

Date Submitted : 03/07/2013

1

1. Literature Review

1.1 State Machines

State machines, also known as finite state machines are circuits that can performs different sets

of sequences of operation controlled by a clock and other inputs.

The state machine can be divided into

(i) Completely specified FSM

(ii) Incompletely specified FSM

Unlike the other, the CS FSM is one which every internal states are defined for each and every

input possibilities.

The type of output of the CSFSM can be categorised as

(i) Mealy Model : where output is dependent upon the present states and the inputs.

(ii) Moore Model : where output is dependent upon present states only.

For designing states machines, once the type of CSFSM has been decided the state diagram showing the

sequence of operation can be obtained and its state table can be easily obtained. Furthermore the state

table can be minimized by using either row matching method or implication chart method. Once the

final state table is obtained designing the system can statrt.

1.2 Programmable Logic Devices (PLD)

A PLD contains a large number of logic gates within a single a package, but allows a user to determine

how they are interconnected; this technology is known as un-committed logic. Since the gate are not

committed to any specific function at the time of manufacture, the various gates within a device and the

interconnections are arranged within one or more arrays. For this reason this form of logic is also known

as array logic. There are many forms of array logic, some of the most widely used include;

a) PLA programmable logic array

b) PAL programmable array logic

c) GAL genetic array logic

d) PROM programmable read only memory

e) CPLD complex programmable logic device

f) FPGA field programmable gate array

1.3 Existing Model

1.3.1 Specification

In this model, a traffic light controller is needed to control the traffic between a main street

and a side street.

2

The main street needs to have green light for 30s followed by 5s transitional caution light

and finally red light. The side street needs to have red light as long as there is green light or

yellow light on the main and green light when the main has a red.

Figure 1.1 Sequence of operation

The table below summarises the sequence and duration

Duration/s Main Side

30 Green (MG) Red (SR)

5 Yellow (MY) Red (SR)

30 Red (MR) Green (SG)

5 Red (MR) Yellow (SY)

Table 1.1 sequence and duration

The controller needs to have six defined outputs and a timer to control the duration of the

lights.

Figure 1.2 Block diagram of the traffic light controller

1.3.2 Steps used in designing the system

1. Timer, T

T has a frequency,f1 , and duty ratio,D, to control sequence duration of 30s followed by 5s.

3

(i) Frequency ,f1

𝑓1 =1

35

= 0.0286 𝐻𝑧

(ii) duty ratio, D

𝐷 = 30

35

= 0.857

When T is high, this corresponds to duration of 30s and when T is low, the duration will be 5s.

Figure 1.3 Timer duration control

2. Finding state equations and output equations.

To find the state equations and output equations the state diagram is required. The controller has four

possibilities of output between the main and side street hence they are defined as states and are

assigned a variable as per the table below.

State Representation

S0 MG and SR

S1 MY and SR

S2 MR and SG

S3 MR and SY

Finally the state diagram is as follows.

Figure 1.4 State Diagram

4

For simplicity only the high outputs of the respective states has been used .

3. State table

The state table is obtained from the state diagram and the states are assigned as per the table

below.

state Binary assignment

Q1 Q0

S0 0 0

S1 0 1

S2 1 0

S3 1 1

TRANSITION TABLE FOR MOORE MACHINE

2. System design

2.1 Moore Model

The new model will designed using the similar concept of the existing model and the

feature to be added is the pedestrian lights. The procedures to be followed are:

1. Find the possible outputs

2. Identify the sequence hence the state diagram

3. State table and excitation table

4. State equations and output equations

5. Logic design

PRESENT STATES

INPUTS NEXT STATES

OUTPUTS

Q1 Q0 T Q1+ Q0+ MR MY MG SR SY SG

0 0 0 0 1 0 0 1 1 0 0

0 0 1 0 0 0 0 1 1 0 0

0 1 0 0 1 0 1 0 1 0 0

0 1 1 1 0 0 1 0 1 0 0

1 0 0 1 1 1 0 0 0 0 1

1 0 1 1 0 1 0 0 0 0 1

1 1 0 1 1 1 0 0 0 1 0

1 1 1 0 0 1 0 0 0 1 0

5

1. According to the specifications the possible outputs are summarised in the table

below

TRANSISTION TIME(T)/SECONDS

MAIN ROAD (M) SIDE ROAD (S) PEDESTRIAN(P)

25 GREEN (G) RED(R) RED(R)

5 YELLOW (Y) RED(R) RED(R)

25 RED(R) GREEN (G) RED(R)

5 RED(R) YELLOW (Y) RED(R)

25 RED(R) RED(R) GREEN (G)

5 RED(R) RED(R) GREEN (G)

2.1 sequence of operation and duration of each states

2.1.2 State Diagram

Fig 2.2 state diagram of the controller

𝑆0

MGSRPR

𝑆1

MYSRPR

𝑆2

MRSGPR

𝑆5

MRSRPY

𝑆3

MRSYPR

𝑆4

MRSRPG

𝑇 = 1/C=X

T=0/C=X

T=1/C=

X

T=0/C=

X

𝑇 =

0/C=X

6

Hence the following state transition table and excitation table are obtained.

NEXT STATES

OUTPUT Z

T C

PRESENT STATES

00 01 10 11

S0 S1 S1 S0 S1 MGSRPR

S1 S1 S1 S2 S2 MYSRPR

S2 S3 S3 S2 S2 MRSGPR

S3 S3 S3 S0 S4 MRSYPR

S4 S5 S5 S4 S4 MRSRPG

S5 S5 S5 S0 S0 MRSRPY

2.1 state transition table for the controller

7

Table 2.2 Excitation table of the controller

From the excitation table the flip flop equations and the output equations can be obtained and

minimised using k-map.

PRESENT STATE INPUT NEXT STATE OUTPUT Flip Flop i/p

Q2 Q1 Q0 T C Q2+ Q1+ Q0+ MR MY MG SR SY SG PR PY PG D2 D1 D0

0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 1

0 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 0 0 0 1

0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0

0 0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0

0 0 1 0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 1

0 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 0 0 0 1

0 0 1 1 0 0 1 0 0 1 0 1 0 0 1 0 0 0 1 0

0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 0 0 0 1 0

0 1 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 1 1

0 1 0 0 1 0 1 1 1 0 0 0 0 1 1 0 0 0 1 1

0 1 0 1 0 0 1 0 1 0 0 0 0 1 1 0 0 0 1 0

0 1 0 1 1 0 1 0 1 0 0 0 0 1 1 0 0 0 1 0

0 1 1 0 0 0 1 1 1 0 0 0 1 0 1 0 0 0 1 1

0 1 1 0 1 0 1 1 1 0 0 0 1 0 1 0 0 0 1 1

0 1 1 1 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0

0 1 1 1 1 1 0 0 1 0 0 0 1 0 1 0 0 1 0 0

1 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 1 0 1

1 0 0 0 1 1 0 1 1 0 0 1 0 0 0 0 1 1 0 1

1 0 0 1 0 1 0 0 1 0 0 1 0 0 0 0 1 1 0 0

1 0 0 1 1 1 0 0 1 0 0 1 0 0 0 0 1 1 0 0

1 0 1 0 0 1 0 1 1 0 0 1 0 0 0 1 0 1 0 1

1 0 1 0 1 1 0 1 1 0 0 1 0 0 0 1 0 1 0 1

1 0 1 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0

1 0 1 1 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0

1 1 0 0 0 X X X X X X X X X X X X X X X








8

1.4 Flip flop input equation and Output equation

𝐷2 = 𝑄2𝑇 + 𝑄2𝑄0 + 𝑄1𝑄0𝑇𝐶

𝐷2 = 𝑄2(𝑇 + 𝑄0) + 𝑄1𝑄0𝑇𝐶

𝐷1 = 𝑄1𝑇 + 𝑄1𝑄0 + 𝑄2 𝑄1𝑄0𝐶

9

𝐷0 = 𝑇

Output Equations

𝑀𝑅 = 𝑄2 + 𝑄1

𝑀𝑌 = 𝑄2 𝑄1𝑄0

𝑀𝐺 = 𝑄2 𝑄1 𝑄0

00 01 11 10

0 0 1 1

1 1 1 X X

00 01 11 10

0 0 1 0 0

1 0 0 X X

00 01 11 10

0 1 0 0 0

1 0 0 X X

Q1Q0

Q2

Q1Q0

Q2

Q1Q0

Q2

Q1Q0

Q2

10

𝑆𝑅 = 𝑄1

𝑆𝑌 = 𝑄1𝑄0

𝑆𝐺 = 𝑄1𝑄0

𝑃𝑅 = 𝑄2

𝑃𝐺 = 𝑄2𝑄0

𝑃𝑌 = 𝑄2𝑄0

00 01 11 10

0 1 1 0 0

1 1 1 X X

00 01 11 10

0 0 0 1 0

1 0 0 X X

00 01 11 10

0 0 0 0 1

1 0 0 X X

00 01 11 10

0 1 1 1 1

1 0 0 X X

00 01 11 10

0 0 0 0 0

1 1 0 X X

00 01 11 10

0 0 0 0 0

1 0 1 X X

Q1Q0

Q2

Q1Q0

Q2

Q1Q0

Q2

Q1Q0

Q2

Q1Q0

Q2

11

2.2 Mealy Model

2.2.1 STATE DIAGRAM

2.2.2 STATE TABLE

TABLE 1.

BINARY ASSIGMENT

STATES

S0 000

S1 001

S2 010

S3 011

S4 100

S5 101

Table 2.3 Binary assignment

SO

S1

S2

S5

S3

S4

T/P=X/

MGSRPR

𝑇 /P=X/

MYSRPR

T/P=X

/

𝑇 /P=X/

MRSYPR

𝑇 /P=X/

MRSRPY

12

Q1Q0 TP Q2=0 Q1Q0

TP Q2=1

Q1Q0 TP Q2=0 Q1Q0

TP Q2=1

2.4 excitation table of mealy model

2.2.3 State Equation

00 01 11 10 00 01 11 10

00 0 0 0 0 00 1 1 1 1

01 0 0 0 0 01 1 1 0 0

11 0 0 1 0 11 0 0 0 0

10 0 0 0 0 10 0 0 0 0

𝐷2 = 𝑄2𝑄1𝑄0 + 𝑄2𝑄1𝑇 + 𝑄2 𝑄1𝑄0𝑇𝑃

00 01 11 10 00 01 11 10

00 0 0 0 0 00 0 0 0 0

01 0 0 1 1 01 0 0 0 0

11 1 1 0 0 11 0 0 0 0

10 1 1 1 1 10 0 0 0 0

𝐷1 = 𝑄2 𝑄1𝑄0 + 𝑄2 𝑄1𝑇 + 𝑄2𝑄1 𝑄0𝑇

PRESENT STATE INPUT NEXT STATE OUTPUT

Q2 Q1 Q0 T P Q2+ Q1+ Q0+ MG MY MR SG SY SR PG PY PR

0 0 0 0 X 0 0 1 1 0 0 0 0 0 0 0 1

0 0 0 1 X 0 0 0 1 0 0 0 0 0 0 0 1

0 0 1 0 X 0 0 1 0 1 0 0 0 0 0 0 1

0 0 1 1 X 0 1 0 0 1 0 0 0 0 0 0 1

0 1 0 0 X 0 1 1 0 0 1 1 0 0 0 0 1

0 1 0 1 X 0 1 0 0 0 1 1 0 0 0 0 1

0 1 1 0 X 0 1 1 0 0 1 0 1 0 0 0 1

0 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0 1

0 1 1 1 1 1 0 0 0 0 1 0 1 0 0 0 1

1 0 0 0 X 1 0 1 0 0 1 0 0 1 1 0 0

1 0 0 1 X 1 0 0 0 0 1 0 0 1 1 0 0

1 0 1 0 X 1 0 1 0 0 1 0 0 1 0 1 0

1 0 1 1 X 0 0 0 0 0 1 0 0 1 0 1 0

13

Q1Q0 TP

Q2=0 Q1Q0

TP Q2=1

Q1Q0 TP Q2=0 Q1Q0

TP Q2=1

Q1Q0 TP Q2=0 Q1Q0

TP Q2=1

Q1Q0 TP Q2=0 Q1Q0

TP Q2=1

𝐷0 = 𝑄2𝑇 + 𝑄1 𝑇

00 01 11 10 00 01 11 10

00 1 1 1 1 00 0 0 0 0

01 0 0 0 0 01 0 0 0 0

11 0 0 0 0 11 0 0 0 0

10 0 0 0 0 10 0 0 0 0

𝑀𝐺 = 𝑄2𝑄1𝑄0

00 01 11 10 00 01 11 10

00 0 0 0 0 00 0 0 0 0

01 1 1 1 1 01 0 0 0 0

11 0 0 0 0 11 0 0 0 0

10 0 0 0 0 10 0 0 0 0

𝑀𝑌 = 𝑄2𝑄1 𝑄0

00 01 11 10 00 01 11 10

00 0 0 0 0 00 1 1 1 1

01 0 0 0 0 01 1 1 1 1

11 1 1 1 1 11 0 0 0 0

10 1 1 1 1 10 0 0 0 0

00 01 11 10 00 01 11 10

00 1 1 0 0 00 1 1 0 0

01 1 1 0 0 01 1 1 0 0

11 1 1 0 0 11 0 0 0 0

10 1 1 0 0 10 0 0 0 0

14

Q1Q0 TP Q2=1 Q1Q0

TP Q2=1

Q1Q0 TP Q2=0 Q1Q0

TP Q2=1

Q1Q0 TP Q2=0 Q1Q0

TP Q2=1

Q1Q0 TP Q2=0 Q1Q0

TP Q2=1

𝑀𝑅 = 𝑄2 𝑄1 + 𝑄2𝑄1

00 01 11 10 00 01 11 10

00 00 0 0 0 0

01 01 0 0 0 0

11 11 0 0 0 0

10 1 1 1 1 10 0 0 0 0

SG=𝑄2 𝑄1𝑄0

00 01 11 10 00 01 11 10

00 0 0 0 0 00 0 0 0 0

01 0 0 0 0 01 0 0 0 0

11 1 1 1 1 11 0 0 0 0

10 0 0 0 0 10 0 0 0 0

SY=𝑄2 𝑄1𝑄0

00 01 11 10 00 01 11 10

00 1 1 1 1 00 1 1 1 1

01 1 1 1 1 01 1 1 1 1

11 0 0 0 0 11 0 0 0 0

10 0 0 0 0 10 0 0 0 0

𝑆𝑅 = 𝑄1

00 01 11 10 00 01 11 10

00 1 1 1 1 00 0 0 0 0

01 0 0 0 0 01 1 1 1 1

11 0 0 0 0 11 0 0 0 0

10 0 0 0 0 10 0 0 0 0

𝑃𝐺 = 𝑄2𝑄1𝑄0 𝑃𝑌 = 𝑄2𝑄1 𝑄0

15

Q1Q0 TP Q2=0 Q1Q0

TP Q2=1

00 01 11 10 00 01 11 10

00 1 1 1 1 00 0 0 0 0

01 1 1 1 1 01 0 0 0 0

11 1 1 1 1 11 0 0 0 0

10 1 1 1 1 10 0 0 0 0

𝑃𝑅 = 𝑄2

16

17

3. Implementation using FPLA

A programmable logic array is a kind of programmable logic device used to implement combinational

circuits. The structure of the PLA is shown in (design of FPLA). This show an arrangement with five inputs

(Q2, Q1, Q0, T, P) which are inverted to produce 5 pairs of complementary inputs. The signals are then

each connected through an array of fusible links. These fuses are initially all intact, but they may be

blown selectively to determine the pattern of connections between the inputs. Signals and the AND

gates. In this way each AND gate corresponds to an individual minterm. A second array of fuses is used

to connect the outputs of the AND gates to a collection of OR gates. These OR gates combine the

relevant minterms to produce various outputs.

In order to represent symbolically the large number of gates and interconnections within a typical

device, it is conventional to adopt a more compact notation that reduces a large number of

interconnecting wires within various array.

The symbols used when drawing logic arrays are shown in (design of FPLA). Here a single line is drawn to

represent all inputs to the gate and a cross used to indicate those inputs lines that are connected to that

gate.

18

The product terms were obtained from the moore model design in section 2

Table 3.1 personality matrix of FPLA

INPUTS OUTPUTS

Product term

Q2 Q1 Q0 T P D2 D1 D0 MG MY MR SG SY SR PG PY PR

𝑄2𝑄1𝑄0 1 0 0 - - 1 - - - - - - - - - - -

𝑄2𝑄1𝑇 1 1 - 0 - 1 - - - - - - - - - - -

𝑄2𝑄0𝑇𝑃 1 1 1 1 1 1 - - - - - - - - - - -

𝑄2𝑄1𝑄0 0 1 0 - - - 1 - - - - - - - - - -

𝑄2𝑄1𝑇 0 1 - 0 - - 1 - - - - - - - - - -

𝑄2𝑄1𝑄0𝑇 0 0 1 1 - - 1 - - - - - - - - - -

𝑄2𝑇 0 - - 0 - - - 1 - - - - - - - - -

𝑄1𝑇 - 0 - 0 - - - 1 - - - - - - - - -

𝑄2𝑄1𝑄0 0 0 0 - - - - - 1 - - - - - - - -

𝑄2𝑄1𝑄0 0 0 1 - - - - - - 1 - - - - - - -

𝑄2𝑄1 0 1 - - - - - - - - 1 - - - - - -

𝑄2𝑄1 1 0 - - - - - - - - 1 - - - - - -

𝑄2𝑄1𝑄0 0 1 0 - - - - - - - - 1 - - - - -

𝑄2𝑄1𝑄0 0 1 1 - - - - - - - - - 1 - - - -

𝑄1 - 0 - - - - - - - - - - - 1 - - -

𝑄2𝑄1𝑄0 1 0 0 - - - - - - - - - - - 1 - -

𝑄2𝑄1𝑄0 1 0 1 - - - - - - - - - - - - 1 -

𝑄2 0 - - - - - - - - - - - - - - - 1

19

Figure 3.2 Design of FPLA

4. Implementation on the GAL

The system to be implemented on the GAL is a sequential circuit. The sequence of

operation from the state table and the output equations obtained from the moore

20

model will be used to program the GAL in wincupl. Since there are 9 outputs 2

G16V8 ICs is used to implement the system.

1.4.1 design file for first IC

On the first IC the flip flop states will be generated and it will also contain the

output for the main red.

(a) Program file

Name ESD ASS ;

PartNo 00 ;

Date 26-Feb-13 ;

Revision 01 ;

Designer Engineer ;

Company UOM ;

Assembly None ;

Location REDUIT ;

Device g16v8 ;

/* *************** INPUT PINS *********************/

PIN 1 = CLK ; /* clock */

PIN 2 = T ; /* duration control

*/

PIN 3 = C ; /* debounce switch

*/

/* *************** OUTPUT PINS *********************/

PIN 12 = Q0 ; /* state outputs

*/

PIN 13 = Q1 ; /* */

PIN 14 = Q2 ; /* */

PIN 15 = MR;

FIELD state = [Q0..2];

$REPEAT i=[0..5] /*******define the states**********/

$DEFINE S{i} 'b'{i}

$REPEND

FIELD MODE=[T,C]; /*********group inputs******/

GO = MODE : 0;

FOLLOW = MODE : 1;

NOPED = MODE : 2;

PED = MODE : 3;

SEQUENCE state { /*********sequence of operations*****/

PRESENT S0

IF GO NEXT S1;

IF FOLLOW NEXT S1;

DEFAULT NEXT S0;

PRESENT S1

IF GO NEXT S1;

IF FOLLOW NEXT S1;

DEFAULT NEXT S2;

PRESENT S2

IF GO NEXT S3;

IF FOLLOW NEXT S3;

DEFAULT NEXT S2;

PRESENT S3

21

IF GO NEXT S3;

IF FOLLOW NEXT S3;

IF NOPED NEXT S0;

IF PED NEXT S4;

PRESENT S4

IF GO NEXT S5;

IF FOLLOW NEXT S5;

DEFAULT NEXT S4;

PRESENT S5

IF GO NEXT S5;

IF FOLLOW NEXT S5;

DEFAULT NEXT S0;

}

MR = Q2#Q1; /* main red output */

1.2 Jedec File for first IC

CUPL(WM) 5.0a Serial# 60008009

Device g16v8ms Library DLIB-h-40-11

Created Mon Mar 04 18:18:26 2013

Name ESD ASS

Partno 00

Revision 01

Date 26-Feb-13

Designer Engineer

Company UOM

Assembly None

Location REDUIT

*QP20

*QF2194

*QV31

*G0

*F0

*L01024 11111111111111111111111111111111

*L01056 11111111111111111111110111111111

*L01088 11111111111111111111111111011111

*L01280 10111111111111111111110111101101

*L01312 01110111111111111111111011011101

*L01344 11111111111111111111110111101110

*L01536 10111111111111111111111011011101

*L01568 01111111111111111111111011101101

*L01600 11111111111111111111111011011110

*L01792 10111111111111111111111011011111

*L01824 10111111111111111111111111101111

*L02048 00001111001100000011000000100000

*L02112 00000000111110001111111111111111

*L02144 11111111111111111111111111111111

*L02176 111111111111111101

*C2F6B

*P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

*V0001 C11XXXXXXNXLLLLXXXXN


*V0003 C01XXXXXXNXHLLLXXXXN


*V0005 C11XXXXXXNXLHLHXXXXN


*V0007 C01XXXXXXNXHHLHXXXXN


*V0009 C11XXXXXXNXLLHHXXXXN

22

*V0010 C11XXXXXXNXLLHHXXXXN

*V0011 C01XXXXXXNXHLHHXXXXN

*V0012 C01XXXXXXNXHLHHXXXXN




















* BC23

1.3 Fuse Plot

**************************************************************************

*****

ESD

**************************************************************************

*****


Device g16v8ms Library DLIB-h-40-11

Created Wed Feb 27 21:29:45 2013

Name ESD ASS

Partno 00

Revision 01

Date 26-Feb-13

Designer Engineer

Company UOM

Assembly None

Location REDUIT

==========================================================================

=====

Expanded Product Terms

==========================================================================

=====

FOLLOW =>

C & !T

GO =>

!C & !T

23

MODE =>

T , C

MR =>

Q2

# Q1

NOPED =>

!C & T

PED =>

C & T

Q0.d =>

Q1 & !Q2 & !T

# !Q1 & !T

Q1.d =>

Q0 & Q1 & !Q2 & !T

# Q0 & !Q1 & !Q2 & T

# !Q0 & Q1 & !Q2

Q2.d =>

Q0 & !Q1 & Q2 & !T

# C & Q0 & Q1 & !Q2 & T

# !Q0 & !Q1 & Q2

state =>

Q0 , Q1 , Q2

MR.oe =>

1

24

==========================================================================

=====

Symbol Table

==========================================================================

=====

Pin Variable Pterms Max Min

Pol Name Ext Pin Type Used Pterms Level

--- -------- --- --- ---- ------ ------ -----

C 3 V - - -

CLK 1 V - - -

FOLLOW 0 I 1 - -

GO 0 I 1 - -

MODE 0 F - - -

MR 15 V 2 7 1

NOPED 0 I 1 - -

PED 0 I 1 - -

Q0 12 V - - -

Q0 d 12 X 2 8 1

Q1 13 V - - -

Q1 d 13 X 3 8 1

Q2 14 V - - -

Q2 d 14 X 3 8 1

T 2 V - - -

state 0 F - - -

MR oe 15 D 1 1 0

LEGEND D : default variable F : field G : group

I : intermediate variable N : node M : extended node

U : undefined V : variable X : extended

variable

T : function

25

==========================================================================

=====

Fuse Plot

==========================================================================

=====

Syn 02192 x Ac0 02193 -

Pin #19 02048 Pol x 02120 Ac1 -

00000 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx








Pin #18 02049 Pol x 02121 Ac1 -









Pin #17 02050 Pol x 02122 Ac1 -









Pin #16 02051 Pol x 02123 Ac1 -









Pin #15 02052 Pol - 02124 Ac1 -

01024 --------------------------------

01056 ----------------------x---------

01088 --------------------------x-----






Pin #14 02053 Pol - 02125 Ac1 x

01280 -x--------------------x----x--x-

01312 x---x------------------x--x---x-

01344 ----------------------x----x---x



26




Pin #13 02054 Pol - 02126 Ac1 x

01536 -x---------------------x--x---x-

01568 x----------------------x---x--x-

01600 -----------------------x--x----x






Pin #12 02055 Pol - 02127 Ac1 x

01792 -x---------------------x--x-----

01824 -x-------------------------x----







LEGEND X : fuse not blown

- : fuse blown

27

==========================================================================

=====

Chip Diagram

==========================================================================

=====

______________

| ESD |

CLK x---|1 20|---x Vcc

T x---|2 19|---x

C x---|3 18|---x

x---|4 17|---x

x---|5 16|---x

x---|6 15|---x MR

x---|7 14|---x Q2

x---|8 13|---x Q1

x---|9 12|---x Q0

GND x---|10 11|---x

|______________|

1.4 Design file for second IC

The second IC will contain the rest of the outputs that is the main yellow and

green,side red,yellow and green and the pedestrian also.

Name output ;

PartNo 00 ;

Date 03-Mar-13 ;

Revision 01 ;

Designer Engineer ;

Company Home ;

Assembly None ;

Location ;

Device g16v8 ;

/* *************** INPUT PINS *********************/

PIN 2 = Q0 ; /*

*/

PIN 3 = Q1 ; /* state

*/

PIN 4 = Q2 ; /* inputs

*/

/* *************** OUTPUT PINS *********************/

PIN [12..19] = [U0..7] ; /*

*/

U0 =!Q2&!Q1&Q0; /*main yellow*/

U1 = !Q2&!Q1&!Q0; /*main green*/

U2 = !Q1; /*side red*/

U3 = Q1&Q0; /*side yellow*/

U4 = Q1&!Q0; /*side green*/

U5 = !Q2; /*pedestrian red*/

U6 = Q2&Q0; /*pedestrian yellow*/

28

U7 = !Q0&Q2; /*pedestrian green*/

1.5 Jedec file


Device g16v8s Library DLIB-h-40-9


Name output

Partno 00

Revision 01

Date 03-Mar-13

Designer Engineer

Company Home

Assembly None

Location

*QP20

*QF2194

*QV27

*G0

*F0

*L00000 10111111011111111111111111111111

*L00256 01111111011111111111111111111111

*L00512 11111111101111111111111111111111

*L00768 10110111111111111111111111111111

*L01024 01110111111111111111111111111111

*L01280 11111011111111111111111111111111

29

*L01536 10111011101111111111111111111111

*L01792 01111011101111111111111111111111

*L02048 11111111001100000011000000100000

*L02112 00000000000000001111111111111111

*L02144 11111111111111111111111111111111

*L02176 111111111111111110

*C2863

*P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

*V0001 X000XXXXXNXLHHLLHLLN


*V0003 X100XXXXXNXHLHLLHLLN


*V0005 X010XXXXXNXLLLLHHLLN


*V0007 X110XXXXXNXLLLHLHLLN


*V0009 X001XXXXXNXLLHLLLLHN

*V0010 X001XXXXXNXLLHLLLLHN

*V0011 X101XXXXXNXLLHLLLHLN

*V0012 X101XXXXXNXLLHLLLHLN







30










* 7D60

4.6 Fuse Plot

**************************************************************************

*****

output

**************************************************************************

*****


Device g16v8s Library DLIB-h-40-9


Name output

Partno 00

Revision 01

Date 03-Mar-13

Designer Engineer

Company Home

Assembly None

Location

==========================================================================

=====

Expanded Product Terms

==========================================================================

=====

U0 =>

Q0 & !Q1 & !Q2

U1 =>

!Q0 & !Q1 & !Q2

U2 =>

!Q1

31

U3 =>

Q0 & Q1

U4 =>

!Q0 & Q1

U5 =>

!Q2

U6 =>

!Q0 & Q2

U7 =>

Q0 & Q2

==========================================================================

=====

Symbol Table

==========================================================================

=====

Pin Variable Pterms Max Min

Pol Name Ext Pin Type Used Pterms Level

--- -------- --- --- ---- ------ ------ -----

Q0 2 V - - -

Q1 3 V - - -

Q2 4 V - - -

U0 12 V 1 8 1

U1 13 V 1 8 1

U2 14 V 1 8 1

U3 15 V 1 8 1

U4 16 V 1 8 1

U5 17 V 1 8 1

U6 18 V 1 8 1

U7 19 V 1 8 1

LEGEND D : default variable F : field G : group

I : intermediate variable N : node M : extended node

U : undefined V : variable X : extended

variable

T : function

32

==========================================================================

=====

Fuse Plot

==========================================================================

=====

Syn 02192 - Ac0 02193 x

Pin #19 02048 Pol - 02120 Ac1 x

00000 x-------x-----------------------








Pin #18 02049 Pol - 02121 Ac1 x

00256 -x------x-----------------------








Pin #17 02050 Pol - 02122 Ac1 x

00512 ---------x----------------------








Pin #16 02051 Pol - 02123 Ac1 x

00768 -x--x---------------------------








Pin #15 02052 Pol - 02124 Ac1 x

01024 x---x---------------------------








Pin #14 02053 Pol - 02125 Ac1 x

01280 -----x--------------------------





33




Pin #13 02054 Pol - 02126 Ac1 x

01536 -x---x---x----------------------








Pin #12 02055 Pol - 02127 Ac1 x

01792 x----x---x----------------------








LEGEND X : fuse not blown

- : fuse blown

==========================================================================

=====

Chip Diagram

==========================================================================

=====

______________

| output |

x---|1 20|---x Vcc

Q0 x---|2 19|---x U7

Q1 x---|3 18|---x U6

Q2 x---|4 17|---x U5

x---|5 16|---x U4

x---|6 15|---x U3

x---|7 14|---x U2

x---|8 13|---x U1

x---|9 12|---x U0

GND x---|10 11|---x

|______________|

34

4.7 Results on winsim

35

Fig 4.1 Results onbtained on Winsim

4.8 Hardware Analysis

Initially the debounce switch input is low and T is varied manually. The first

output is that of state S0 that is MG,SR and PR is high.

The last LED will be used for the PG and PY output since the board contain an LED less than the

controller. Then T is set low and state S1 is obtained.

State S1

T is set high and the following output is obtained

State S2

36

T is then set low.

State S3

T is set high

State S0

After this state debounce switch input is set high.

State S1

State S2

State S3

37

State S4

The last LED is representing the PG output and the PY was low when tested.

State S5

Last LED representing PY and PG was low.

The two ICs of 20 pins were placed in the IC test socket of 40 pins. For the first IC, pin number 0 to 10 of the IC test socket represents pin number 0 to 10 of the IC. Pin 31 to 40 of the IC test socket corresponds to the pin number 11 to 20 of the first IC. For the second IC pin 1 to 10 corresponds to 11 to 20 of the IC test socket and 11 to 20

corresponds to 21 to 30 of the IC test socket. The table below summarises the pin relationship

between the Ics and the IC test socket.

IC Pins IC test socket Pins

first 1 – 10 1 – 10

11 – 20 31 – 40

second 1 – 10 11 – 20

11 – 20 21 – 30

Table 4.1 Pins relationship between IC and IC test socket

38

APPENDIX

Datasheets for Quad 2-input AND Gate (74LS08)

39

40

APPENDIX A3

Datasheet for 3-input AND Gate(74LS11)

41

42

APPENDIX A4

Datasheet for Dual 4-input AND Gate (74LS21)

43

44

APPENDIX A5

Datasheet for Quad-2 input OR Gate (74LS32)

45

46

47

48

49

Datasheet for Quad D flip flop(74LS175)

50

51

52

Datasheet for gal16v8:

53

54

Datasheet for NE 555 Timer

55