Vedic

VHDL Code of Vedic Multiplier

with Minimum Delay ArchitecturePresented By

Vaibhav Jindal

Gautam Buddha University

1

Contents

Introduction

Vedic Method 1 (Urdhva Tiryakbhyam)

Architecture based on Urdhva Tiryakbhyam



Delay Calculation of Architecture

Conclusion

References

2

Introduction

Vedic mathematics is the name given to the ancient system of mathematics, which was

rediscovered, from the Vedas between 1911 and 1918 by Sri Bharati Krishna Tirthaji.

The Vedic multiplication has 16 sutras.

Urdhva-tiryakbhyam -Vertically and crosswise.

3

Introduction

Pdsum= PdXOR & Pdcarry=PdAND Pdsum=2*Pdxor & Pdcarry=PdXOR+PdAND+PdOR

4


Method -1 of 4-bit Vedic Multiplier

5


Architecture 1 for Method1

6

Architecture(Hardware Reduce) based on Urdhva

Tiryakbhyam

Architecture 2 for Method1

7


Method -2 of 4-bit Vedic Multiplier

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Architecture 1 for Method 2

9

Architecture(Hardware Reduce) based on Urdhva

Tiryakbhyam

Architecture 2 for Method 2

10

Delay Calculation of Architectures

Delay Manually

calculated

Slice

Occupied

Total

Delay

(ns)

Method1

Arch.1

PdAND+11xPdHA

+5xPdOR

20 14.310

Method1

Arch.2

PdAND+10xPdHA

+4xPdOR

19 13.155

Method2

Arch.1

PdAND+47xPdHA

+15xPdOR

20 17.829

Method2

Arch.2

PdAND+23xPdHA

+6xPdOR

19 15.779

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Delay calculation on Xilinx (Spartan 3E) Device XC3S500E

Delay Calculation of Architecture

9.4188.714

11.530

10.122

4.8924.441

6.3625.657

14.310

13.155

17.892

15.779

Method1 Arch.1 Method1 Arch.2 Method2 Arch.1 Method2 Arch.2

Logic Delay Root Delay Total Delay

12

Conclusion

The architecture of metho1 with reduce hardware has the less delay

than others architecture.

So, it will enhancing the ability of process or the time of process

will be as low as possible.

13

References

Kabiraj Sethi and Rutuparna Panda, “An Improvedsquaring Circuit For Binary Numbers”,International Journal of Advanced Computer Science and Applications, Vol. 3, 2012.

Purushottam D. Chidgupkar and Mangesh T. Karad, “The Implementation of Vedic Algorithms inDigital Signal Processing”, 7th UICEE Annual Conference on Engineering Education,Global J.of Engng. Educ., Vol.8, 2012.

PoornimaM,shivraj Kumar Patil, Shivkumar, Shridhar K P and Sanjay H, “Implementation ofMultiplier using Vedic Algorithm”, International Journal of Innovative Technology andExploring Engineering, Vol.2, 2013.

Premananda B.S., Samarth S. Pai, Shashank B.,Shashank S. Bhat, “Design and Implementationof 8-Bit Vedic Multiplier”, International Journal of Advanced Research in Electrical, Electronicand Instrumentation Engineering, Vol.2, 2013.

R.Shridevi, Anirudh Palakurthi, Akhila Sadhula, Hafsa Mahreen, “Design of a High SpeedMultiplier (Ancient Vedic Mathematics Approach) ” International Journal of EngineeringResearch, Vol.2, 2013.

14

Thanks’

Questions ?15