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Analog Integrated Circuits and SignalProcessingAn International Journal ISSN 0925-1030 Analog Integr Circ Sig ProcessDOI 10.1007/s10470-012-9979-4

Analog baseband chain of syntheticaperture radar (SAR) receiver

Faizah Abu Bakar, Qaiser Nehal, PekkaUkkonen, Ville Saari & Kari Halonen

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Analog baseband chain of synthetic aperture radar (SAR) receiver

Faizah Abu Bakar • Qaiser Nehal • Pekka Ukkonen •

Ville Saari • Kari Halonen

Received: 3 April 2012 / Revised: 10 October 2012 / Accepted: 10 October 2012

� Springer Science+Business Media New York 2012

Abstract An analog baseband chain for a synthetic

aperture radar receiver implemented in a 130 nm CMOS

technology is presented in this paper. Occupying 0.23 mm2

of silicon area, the baseband chain consists of a three-stage

variable gain amplifier (VGA), a 5th-order gm-C low-pass

filter (LPF) and an output buffer. The gain of the chain can

be controlled by tuning the control voltages of the VGA

and has a range from 25 to 34 dB. 8 dB of the gain is

embedded into the LPF. The bandwidth of the LPF is

programmable from 100 to 190 MHz by means of capac-

itor matrices. The chain, which uses a 1.2 V supply volt-

age, achieves an input-referred noise density of 4 nV/ffiffiffiffiffiffi

Hzp

and an in-band IIP3 of -46 dBV rms.

Keywords Analog baseband chain � Synthetic aperture

radar receiver � Variable gain amplifier � Low-pass filter �Output buffer

Abbreviations

SAR Synthetic aperture radar

VGA Variable gain amplifier

LPF Low-pass filter

OBUF Output buffer

ICs Integrated circuits

LNA Low-noise amplifier

ADC Analog-to-digital converter

NMCs Negative Miller capacitors

PVT Process, voltage and temperature

CMFF Common-mode feedforward

CMFB Common-mode feedback

1 Introduction

Because of insensitivity to weather conditions to process

images day and night, SAR is playing a major role in earth

observation [1]. For a high resolution, wide swath image,

the receive antenna is comprised of multiple parallel con-

nected sub-apertures (i.e. multiple individual receive cells).

To overcome the performance and reliability limitations

and to reduce the size and power consumption of con-

ventional, potentially high complexity, microwave receive

circuits, it is advantageous to realize these receive cells

with integrated circuits (ICs). For example, the low-noise

amplifier of the receive cell can be implemented on a single

IC by using advanced GaN technologies while all the

remaining receiver blocks can be implemented on another

IC in a CMOS technology, as depicted in Fig. 1.

A wideband high-performance analog baseband chain

implemented in a 130 nm CMOS technology for such a

SAR receive cell is described in this paper. This paper is

an extended version of the similar baseband chain which

has been reported in [2]. In this paper, the specifications

needed for the SAR receiver is briefly described to clarify

the performances achieved by the circuits. In addition, the

design strategy of the variable gain amplifier (VGA) is

explained in the aim to achieve a low input-referred noise

of the baseband chain. A more detail circuit description

and figure of the output buffer (OUBF) is also presented.

Besides, key measurement results plotted overlaps with

the simulation results are added to confirm the measured

F. Abu Bakar (&) � Q. Nehal � P. Ukkonen � V. Saari �K. Halonen

Department of Micro and Nanosciences, School of Electrical

Engineering, Aalto University, P.O. Box 11000, 00076 Aalto,

Finland

e-mail: [email protected]

123

Analog Integr Circ Sig Process

DOI 10.1007/s10470-012-9979-4

Author's personal copy

data. Additional measurement figures have also been

included and a brief explanation about the IIP3 mea-

surement is defined. Moreover, comparison of perfor-

mances between this chain are done with more reported

baseband chains.

Since this work is targeted for the specific application

(SAR receiver), the specifications are shortly explained

here. In this SAR-application, the band of operation is

bandpass filtered in the radiator panel. Therefore, it is

assumed that the bandpass filter will attenuate unwanted

out-of-band interfering signals before the integrated

receiver. Consequently, a reduced linearity of the analog

baseband chain might not be a problem. In this targeted

integrated receiver, the voltage gain and the noise figure

of the RF front-end can be assumed to be 20 and 8 dB

respectively, meanwhile the maximum input power at

the receiver input is specified to be -46 dBm. Hence, the

gain needed by the analog baseband chain to achieve the

desired full-scale voltage at the analog-to-digital converter

(ADC) input of 800 mV pp, diff is 28 dB, which, from

basic calculation, made it feasible to achieve maximum of

-33 dBV rms in-band IIP3. Additionally, assuming the

analog baseband circuit is allowed to increase the noise

figure of the whole integrated receiver to 10 dB, it can

be calculated the high limit for the input-referred

noise density of the baseband circuit is approximately

11.5 nV/ffiffiffiffiffiffi

Hzp

.

The paper is organized as follows. Section 2 describes

the receiver architecture. Section 3 presents the circuit

design of each circuit block, a VGA, low-pass filter

(LPF), and OBUF. The measured performance of the

circuit is reported in Sect. 4 and conclusions are presented

in Sect. 5.

2 Receiver architecture

The integrated SAR receiver under development employs a

direct conversion architecture. The analog baseband chain

of the receiver consists of a 1 GHz VGA, a 190 MHz LPF

and an OBUF as shown in Fig. 1.

In a direct-conversion receiver, the noise of the analog

baseband circuit typically has a significant effect on the

total noise figure of the receiver. Owing to the moderate

gain of the RF front-end, the baseband chain is required to

have several dBs of gain, as stated previously, in order to

amplify received in-band signals to the desired full-scale

level of the following ADC. In this design, the VGA is

placed at the baseband input to provide most of the gain

and, hence, to reduce the noise contribution of the sub-

sequent receiver blocks. The baseband circuit also includes

a DC offset compensation circuit to overcome DC offset

errors. The LPF following the VGA is needed to perform

the anti-aliasing filtering before signal digitization.

According to simulations, the selectivity requirement can

be met with a 5th-order low-pass filter. In addition to the

selectivity, the flatness of the filter magnitude response is

crucial in the targeted wideband SAR application. The

OBUF is designed to drive a high-resolution ADC, for

example a similar ADC as reported in [3].

3 Circuit descriptions

3.1 Variable gain amplifier

Three important requirements for the VGA are wide

bandwidth, low noise and a tunable gain. The VGA should

90º

0º

LPF

LPF

ADC

ADC

Test out/in

Test out/in

VGA

VGA

OBUF

OBUF

Quadraturemixer

Bias &control

RFinInput buffer

LO

Clock

Clock

Analog baseband chain

This work

LNA

DSP

IC in CMOS technology

Fig. 1 SAR receiver


123


have 1 GHz bandwidth over its entire gain tuning range.

This ensures that the shape of the filter response is not

affected by the VGA. Since most of the gain for baseband

amplification comes from VGA, its input-referred noise

density determines the overall input-referred noise of the

baseband. In order to meet these requirements, the fol-

lowing design approach was adopted. The amplifier was

divided into three design blocks: the low-noise input stage,

two variable gain stages and a DC-offset correction feed-

back stage as shown in Fig. 2. In order to get a good noise

performance at all gain settings, the input stage was

designed to a have a fixed gain. By keeping the gain of the

input stage much higher than the gain of the remaining two

stages, the noise from the input stage dominates the overall

input-referred noise of the VGA [4].

The VGA shown in Fig. 2, consists of three gain stages

VGA 1, VGA 2, VGA 3, and a DC offset correction net-

work. The negative DC feedback network removes the DC

offset voltage originating from the RF front-end and the

device mismatches in the VGA.

The first gain stage shown in Fig. 3, is a fixed gain,

resistively loaded source coupled pair. It uses negative

Miller capacitors (NMCs) (Cc1a and Cc1b) to cancel the

parasitic gate-drain capacitances (Cgd1a and C gd1b) of M1a

and M1b [5]. This reduces the input capacitance of the VGA

and the capacitive load of the mixer. Since the VGA stages

are dc coupled to each other, a common-mode feedback

amplifier is used in each stage to stabilize the output dc

voltage of each stage against process, voltage and tem-

perature (PVT) variations. Assuming that NMCs (Cc1a and

Cc1b) completely cancel the parasitic gate-drain capaci-

tances (Cgd1a and Cgd1b) of M1a and M1b, the voltage gain

of VGA 1 can be written as

AvðsÞ � � gm1aRD1s

sRg1Cgs1a þ 1� �

sRD1aCL1 þ 1ð Þð1Þ

where Rg1 represents the output resistance of the preceding

mixer and CL1 represents the equivalent load capacitance at

the node VOUT1.

The next two stages VGA 2 and VGA 3, are variable

gain degenerated differential pairs shown in Fig. 4. Here

again NMCs (Cc2a and Cc2b) are used to reduce the input

capacitance of these stages. The net result of the use of

NMCs is that the overall bandwidth of the VGA is 1 GHz

over the entire gain tuning range. Assuming that the NMCs

(Cc2a and Cc2b) completely cancel the parasitic gate-drain

capacitances (Cgd2a and Cgd2b) of M2a and M2b, the voltage

gain of VGA2 (or VGA 3) can be written as

AvðsÞ � �gm2aRD2a

swz1þ 1

� �

1þ gm2aRs

2

� �

swp1þ 1

� �

swp2þ 1

� �

swp3þ 1

� � ð2Þ

where

wz1 ¼1

RsCsð3Þ

VGA 1 VGA 2 VGA 3 Buffer

gmf

RF

RF

CF CF

DC Offset Correction

VIN VOUT

SubthresholdResistorTo VGA 1

VDC+VDC-

Feedback Amplifier

LOW NOISEINPUT STAGE

TWO VARIABLEGAIN STAGES

DC-OFFSET CORRECTION FEEDBACK LOOP

INPUT OUTPUT

(a) (b)

Fig. 2 a Design strategy for VGA. b Block diagram of the fully differential three-stage VGA

M1a M1b

VDD

Cc1a Cc1b

Cf

M5 VCM

RCM1 RCM2 VCMFB

VOUT1

VIN1+ VIN1-

Rg1 Rg1

CL1

RD1a RD1b

CL1

CMFB Amplifier

Fig. 3 Schematic of the VGA stage 1


123


wp1 ¼1þ gm2aRs=2ð Þ

Rg2Cgs2a þ Rs Cs þ Cgs2a=2� �� ð4Þ

wp2 ¼1

RsCsþ 1

Rg2Cgs2aþ 1

2Rg2Csð5Þ

wp3 ¼1

RD2aCL2

ð6Þ

In (4) and (5) Rg2 represents the source resistance of the

driving input source and in (6) CL2 represents the equiva-

lent load capacitance at the node VOUT2. The zero wz1

resulting from the capacitive degeneration can be made to

cancel the pole wp1. In this case the voltage gain of (2) can

be rewritten as

AvðsÞ � � gm2aRD2a

1þ gm2aRs

2

� �

swp2þ 1

� �

swp3þ 1

� � ð7Þ

The voltage gain of VGA 2 (or VGA 3) can be varied by

changing the value of Rs as can be seen from (7). Figure 4

shows that Rs can be implemented as a cascade connection

of transistors. Therefore, the gate voltage Vgate of these

transistors can be used to change the voltage gain. It must

be noted that changing the value of Rs also affects the pole-

zero cancellation of wz1 and wp1. Therefore the capacitor Cs

is realized as a switchable capacitor matrix to ensure

proper pole-zero cancellation.

The low-pass RFCF pole in the feedback path with a cut-

off frequency of 10 kHz is employed for DC offset

correction. A low cut-off frequency is essential in the tar-

geted radar application in order to avoid a loss of infor-

mation as a result of the formed high-pass filtering. PMOS

transistors in subthreshold are used to emulate very high

resistance and thus reduce the chip area. The linearity of

this high resistance RF can be improved by cascading

several PMOS devices together. This ensures that the

change in the equivalent resistance value is reduced over a

large voltage variation. The output of VGA 3 is connected

to the low-pass RFCF pole. The amplifier gmf senses the

output voltage from the low-pass RFCF pole and then

generates a correction current to the output of the VGA 1 to

compensate for the DC offset.

3.2 Low-pass filter

The implemented low-pass filter is a 5th-order Chebyshev

prototype with a 0.3 dB passband ripple. The passband-

edge frequency of the filter is programmable from 120 to

190 MHz with 5-bit binary-weighted switched-capacitor

matrices. This wideband LPF is responsible for accom-

plishing anti-aliasing filtering before the analog-to-digital

conversion.

The filter is realized as a continuous-time gm-C leapfrog

filter. Because there is no feedback which translates to a

more simpler circuit, this technique is the most popular

approach to implement on-chip high frequency filter.

VDD

Cf

VCM

RCM2 VCMFB

Cf

Rs

Cs

M6a M6b

M2a M2bVIN2+ VIN2-

VOUT2

Cc2a Cc2b

RCM1

Vgate

Cs1

Cs2

Cs3

Switchable Capacitor Matrix

Realization of Rs Rg2 Rg2

CL2 CL2

RD2a RD2b

CMFB Amplifier

Fig. 4 Schematic of the VGA

stage 2 (or stage 3)


123


Although the linearity performance for this kind of filter is

reduced, it might be no harm since signals are assumed to

have been bandpass filtered in the radiator panel, as briefly

explained before. The filter was synthesized using a lossy

prototype as presented in [6], and uses similar filter

topology as in [7]. The load resistance is removed from the

RLC prototype to minimize the loss of the last filter stage

as described in [6]. As opposite to [7], in this filter design,

all poles are realized using the leapfrog topology (signal

flow graph method), resulting in a simpler structure as

shown in Fig. 5.

The transconductor uses a pseudo-differential topology,

as depicted in Fig. 6. Since no internal poles are present,

this simple structure is suitable for a wideband filter. A

common-mode feedforward circuit is included to obtain

input common-mode rejection, and a common-mode

feedback (CMFB) circuit to fix the output common-mode

voltage of the transconductor. Since the approach used is to

accept a low DC gain for the transconductors, all filter

transconductors are designed to have a nominal gain of

26 dB.

One major issue with a high frequency filter is the

flatness of the magnitude response throughout the pass-

band. In this filter design, five factors are affecting the

frequency response of the filter. The factors are:

1. The accuracy of the DC gain of the transconductors.

2. The biasing accuracy of the transconductor which is

mandatory for an accurate gm value.

3. The ron resistance of the switches used in the capacitor

matrices, affecting the Q factor of the capacitor

matrices.

4. The parasitic capacitances in the filter.

5. The leakage of the NMOS switches.

The transconductor’s gain varies as a result of PVT

variation. This variation is controlled by a negative resis-

tance circuit, which is connected at the output of each

transconductor. The negative resistance circuits are able to

control the DC gain of the transconductors to achieve the

desired 26 dB in all process and temperature corners by

means of a control voltage. A test integrator with a nega-

tive resistance circuit is implemented on a chip to measure

k1gm gm gm gm gm

gmgmgmgmgm

Vin+

Vin-

Vout+

Vout-

Fig. 5 5th-order gm-C low-pass filter

CMFB

INP INN

OUTN OUTP

CMFF

INP

INP

INN

INN

CMFF

gm

gm

INP

INP

INN

INN

OUTP

OUTP

OUTN

OUTN

Vdd

M1

M2

M3

M4

M5

M6

V ERROR

Fig. 6 Transconductor circuit


123


the correct control voltage for the negative resistance

circuits.

As a result of the finite (i.e. non-zero) output conduc-

tance of the transistors, a systematic error exists in the

PMOS current mirror of the transconductors. The amount

of the error is not constant for different process corners and

temperatures. The mirror error can be modeled as a small

common-mode current that is injected into the transcon-

ductor output thereby leading to a shift in the output

common-mode voltage of the transconductor [7]. Since the

transconductance of the pseudo-differential transconduc-

tors depends on the input common-mode level, accurate

biasing is essential in this filter design. A mirror-error

compensation circuit which adds the common-mode error

with reverse polarity to the common-mode reference signal

is designed as shown in Fig. 7. The common-mode level

errors in the transconductors are cancelled by feeding the

reverse-polarity common-mode reference signal to the

V_ERROR gate at the CMFB circuit.

To provide 8 dB of gain, the first feedforward trans-

conductor is scaled by 4. With this scaling, the effective Q

factor of the first filter stage is lower than the Q factor of

the other filter stages as derived from [7]:

Q1;eff ¼ADC

ADC þ 1þ k1

where k1 ¼ 4 ð8Þ

The Q factor of the other filter stages is equal to the DC

gain value of the transconductors.

3.3 Output buffer

The input capacitance of the ADC is in the same order of

magnitude (&400 fF) with the load capacitor of the last

filter stage. Therefore, the OBUF is needed after the LPF to

drive the ADC. A single-stage OBUF with balanced

NMOS input transistor pair is designed, as shown in Fig. 8.

Instead of active loads, it has resistive loads to improve the

in-band linearity of the whole baseband chain. The voltage

gain of the OBUF, determined by the transconductance of

M1 and the load resistance R1, is designed to be 1 dB.

Because the following ADC, that is similar to the one

reported in [3], operates with a 700 mV common-mode

bias voltage, the OBUF also includes a VCM control cir-

cuit at its output.

4 Measurement results

The analog baseband chain was fabricated in a 130 nm

CMOS process, and bonded directly to a 4-layer PCB. A

micrograph of the circuit is shown in Fig. 9. One baseband

chain occupies 0.23 mm2 of silicon area.

Figure 10 depicts the measured and simulated magni-

tude responses of the chain at nominal gain setting. The

nominal gain measured and simulated is around 30 dB.

The measured and simulated magnitude responses of the

chain at different gain settings are shown in Fig. 11. The

measured gain range is 9 dB, 1 dB less than the simulated

gain range.

Figure 12 presents the measured and simulated pro-

grammability of the bandwidth. The measured minimum

and maximum bandwidths achieved are 100 and 190 MHz,

respectively, resulting in a frequency tuning range of

90 MHz, which is in line with the simulated results.

The gain and phase balance between the I and Q paths is

an important parameter for the demodulation of the analog

signal. I/Q imbalance measurements have been obtained by

VCM

VCM

Vdd

VCM

M1

M2

M3

M4

VCM

INPINN OUTN

OUTPTransconductor

Replica circuit

VERROR

VERROR

Fig. 7 Mirror-error

compensation circuit

VSS

−+

VDD

R3R3

M2 M3

VCM

OUTN

IREF

INP

OUTP

INNM1

R1 R1

VCM CONTROL CIRCUIT

M1 M2

M4 M4

Fig. 8 Output buffer


123


the use of mixed-mode S-parameters. Shown in Fig. 13, the

magnitude imbalance is less than ±0.4 dB and the phase

imbalance is ±5� in the passband. The imbalance increases

near the corner frequency due to the slight difference in the

passband-edge frequency between both branches.

Figure 14 shows the measured input-referred noise

density of the chain. A low input-referred noise density of

4 nV/ffiffiffiffiffiffi

Hzp

is achieved as a result of low noise performance

of the VGA.

The in-band IIP3 was measured with 80 and 85 MHz

test signals. The measured in-band IIP3 of the chain is

-46 dBV with the nominal gain of 30 dB (that corre-

sponds to 20.4 dB gain when the losses of the test setup

are not taken into account), as shown in Fig. 15. The

result is due to the high signal swing at the input of LPF.

The high input signal swing causes the LPF to compress

the signal at its output, resulting in a degraded IIP3

performance.

Fig. 9 Baseband micrograph

10 100 200 400 0

5

10

15

20

25

30

35

40

Frequency [MHz]

Mag

nit

ud

e [d

B]

MeasuredSimulated

20 30 100 190 35028

29

30

31

32

Fig. 10 Measured and

simulated magnitude responses

with nominal gain setting


123


10 100 200 400 10

15

20

25

30

35

40

Frequency [MHz]

Mag

nit

ud

e [d

B]

MeasuredSimulated


simulated magnitude responses

with different gain settings

10 100 200 400 0

5

10

15

20

25

30

35

40

Frequency [MHz]

Mag

nit

ud

e [d

B]

MeasuredSimulated


simulated bandwidth

programmability

108

−0.4

−0.2

0

0.2

0.4

dB

Magnitude IQ imbalance (dB)

108

−10

−5

0

5

10

Frequency (Hz)

degr

ees

Phase IQ imbalance (deg)

Fig. 13 IQ imbalance


123


Simulated magnitude response of VGA is shown in

Fig. 16. It has more than 1 GHz bandwidth with variable

gain from 10 to 30 dB.

Table 1 summarizes the performance of the chain pre-

sented in this paper and compares it to other reported

measured baseband chains. It should be noted that the

measured parameters are not directly comparable since

they depends on the targeted SAR receiver application.

5 Conclusions

An analog baseband chain aimed at a direct-conversion

SAR receiver is presented in this paper. The chain has

variable gain from 25 to 34 dB. The baseband chain has a

VGA to supply most of the gain, a 5th-order gm-C as an

anti-aliasing filter and an OBUF to drive a high-resolution

ADC. The filter corner frequency can be tuned from 100 to

190 MHz using switched-capacitor matrices. The achieved

I and Q magnitude and phase imbalance is small in the

passband with less than ±0.4 dB in magnitude and within

±5� in phase. The circuit has also a low input-referred

noise density of 4 nV/ffiffiffiffiffiffi

Hzp

. The achieved measurement

results fulfill the specifications needed for the baseband

chain of the targeted SAR receiver, except for the in band

IIP3 which is worse than expected.

1M 10M 100M 500M1

2

3

4

5

6

7

8

9

10

Frequency [Hz]

Inp

ut−

refe

rred

no

ise

den

sity

[n

V/s

qrt

(Hz)

]

Fig. 14 Measured noise-

density

−70 −65 −60 −55 −50 −45 −40 −35 −30 −25 −20−50

−40

−30

−20

−10

0

Input Power (dBVrms)

Ou

tpu

t P

ow

er (

dB

Vrm

s)

Fundamental output powerThird order intermodulation output power

Fig. 15 Measured in-band

linearity

106

107

108

109

0

5

10

15

20

25

30

35

Frequency (Hz)

Gai

n (d

B)

Vgate = 0.60Vgate = 0.628Vgate = 0.65Vgate = 0.679Vgate = 0.713Vgate = 0.768Vgate = 0.885

Fig. 16 Simulated magnitude response of VGA


123


Acknowledgments This work is supported by European Space

Agency (ESA).

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Faizah Abu Bakar was born in

Selangor, Malaysia in 1980. She

received her B.Eng (Computer

Engineering) and M.Eng (Electri-

cal-Electronic Engineering) from

University of Technology Malay-

sia in 2003 and 2008, respectively.

She is currently working towards

her Doctoral degree in Aalto Uni-

versity, School of Electrical

Engineering, Finland. Her

research interest includes design

and analysis of integrated filters.

Qaiser Nehal received his B.Sc.

(honors) degree in Electrical

Engineering from University

of Engineering & Technology,

Lahore Pakistan in 2007 and his

M.Sc. degree (with distinction)

from Aalto University in 2011. He

joined University of California,

Los Angeles in 2011 where he is

working towards his Ph.D. degree.

His research interests include

analog and RF IC design for

wireless communications.

Table 1 The baseband performance summary

References This work [8] [9] [10] [11] [12]

Process 130 nm 90 nm 180 nm 130 nm 130 nm 180 nm

Supply voltage (V) 1.2 1.4 1.8 1.2 1.2 1.8

Filter order 5 6 6 6 5 3

Gain (dB) 25–34 13.5–67.5 10–55 -9–73 6–48 0–15

Passband edge

frequency

100 to 190 MHz 10 and 100 MHz 264 MHz 250 to 300 MHz 264 and 132 MHz 150 to

1 GHz

Input-referred noise

density4 nv/

ffiffiffiffiffiffi

Hzp

(at nominal

gain)

19 nV/ffiffiffiffiffiffi

Hzp

(at

high gain)

– 1.42 nV/ffiffiffiffiffiffi

Hzp

(at

14 dB gain)

1.42 nV/ffiffiffiffiffiffi

Hzp

z –

In band IIP3 -46 dBVrms (at

nominal gain)

2 dBm (at high

gain)

– -71 dBV (at 73 dB

gain)

10 dBm (at

minimum gain)

–

Power consumption

(mW)

46 13.5 – 60 18 0.12

Active silicon area 0.23 mm2 0.55 mm2 1.25 mm2 0.8 mm2 0.15 mm2 0.2 mm2


123


Pekka Ukkonen received the

B.Sc. degree in electrical engi-

neering from the Aalto Univer-

sity School of Science and

Technology, Espoo, Finland, in

2010. He is currently writing his

Master’s thesis on analog inte-

grated delay equalizer for the

M.Sc. degree.

Ville Saari received the Master

of Science and Licentiate of

Science degrees in electrical

engineering from the Helsinki

University of Technology

(TKK), Finland, in 2002 and

2006, respectively. In 2011, he

received the Doctor of Science

degree in electrical engineering

from the Aalto University, Fin-

land. From 2001 to 2009 he was

with the Electronic Circuit

Design Laboratory, Helsinki

University of Technology, Fin-

land, and from 2010 to 2011

with the Department of Micro- and Nanosciences at the Aalto Uni-

versity, Finland, working on integrated receivers for wireless

applications. In 2010, he was an External Researcher at the Nokia

Research Center, Helsinki, Finland. Since March 2011, he has been a

Senior Design Engineer with the EPCOS Nordic Oy, Espoo, Finland,

focusing on the product development of RF front-end modules for

wireless applications. He has authored or co-authored more than 25

refereed international journal and conference papers.

Kari Halonen received the

M.Sc. degree in electrical engi-

neering from the Helsinki Uni-

versity of Technology, Finland,

in 1982, and the Ph.D. degree in

electrical engineering from the

Katholieke Universiteit Leuven,

Belgium, in 1987. Since 1988

he has been with the Electronic

Circuit Design Laboratory,

Helsinki University of Tech-

nology. From 1993 he has been

an associate professor, and since

1997 a full professor at the

Faculty of Electrical Engineer-

ing and Telecommunications. He became the Head of Electronic

Circuit Design Laboratory in 1998 and he was appointed as the Head

of Department of Micro and Nano Sciences, Aalto University, in

2007. He specializes in CMOS and BiCMOS analog and RF inte-

grated circuits, particularly for telecommunication and sensor appli-

cations. He is author or co-author over 300 international and national

conference and journal publications on analog and RF integrated

circuits.


123
