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8237 / 8257 DMA - DIRECT MEMORY ACCESS
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AJAL.A.J Assistant Professor –Dept of ECE,
UNIVERSAL ENGINEERING COLLEGE
Mob: 8907305642 MAIL: [email protected]
•The DMA I/O technique provides direct access to
the memory while the microprocessor is
temporarily disabled.
Three ways to synchronize the Three ways to synchronize the processor to data rate of processor to data rate of
peripheralsperipherals::1- Polling: which provides a fast response but it the
processor recourses are dedicated to one peripheral.
2- Interrupt approach: is much more efficient. the processor only services the peripheral when data is required. requires high software overhead.
3-DMA is a third solution but it increases the complexity of the hardware system.
DMADMA• Direct Memory Access.• In memory-memory or memory-peripherals communication, the
processor is a “middleman” which is not really needed.
• Used with HOLD HOLDA signals.
• DMA requires another processor - The DMA Controller or DMAC- to generate the memory and I/O addresses.
• 8237 is a DMAC.
• In IBM PC, 8237 was used to speed up the read or write operation by the slow 8088 processor.
• Nowadays, It is usually used by sound cards and by memory controllers to generate row address for refreshing.
I/O Data TransferI/O Data Transfer
Direct memory access (DMA) is a feature of modern computer systems that allows certain hardware subsystems to read/write data to/from memory without microprocessor intervention, allowing the processor to do other work.
Used in disk controllers, video/sound cards etc, or between memory locations.Typically, the CPU initiates DMA transfer, does other operations while the transfer is in progress, and receives an interrupt from the DMA controller once the operation is complete.
Can create cache coherency problems (the data in the cache may be different from the data in the external memory after DMA)
Basic DMA concept
DMA channel: system pathway used by a device to transfer information directly to and from memory. There are usually 8 in a computer systemDMA controller: dedicated hardware used for controlling the DMA operationSingle-cycle mode: DMA data transfer is done one byte at a timeBurst-mode: DMA transfer is finished when all data has been moved
BASIC DMA TERMINOLOGYBASIC DMA TERMINOLOGY
8
DMA pins and timingDMA pins and timing• x86 Interrupt Pins
– HOLD: DMA request.
• Sampled in the middle of any clocking cycle
– HLDA: DMA acknowledge signal.
• The address, data and control buses are set to high-Z,
so the I/O devices can control the system bus
1 2 3 4 5 6 7 8 9
CLK
HOLD
HLDA
9
DMA on the 8086 DMA on the 8086 MicroprocessorMicroprocessor
• The CPU may have to wait (hold cycles).• The DMA will then let the device that requested the DMA transfer know
that the transfer is commencing by asserting the -DACK signal.• Once the data has been transferred, The DMA will de-assert the -DACK2
signal, so that the FDC knows it must stop placing data on the bus.• The DMA will now check to see if any of the other DMA
channels have any work to do. If none of the channels have their DRQ lines asserted, the DMA controller has completed its work and will now tri-state the -MEMR, -MEMW, -IOR, -IOW and address signals.
• Finally, the DMA will de-assert the HOLD signal. The CPU sees this, and de-asserts the HOLDA signal. Now the CPU resumes control of the buses and address lines, and it resumes executing instructions and accessing main memory and the peripherals.
10
8237 pins8237 pins• CLK: System clock• CS΄: Chip select (decoder output)• RESET: Clears registers, sets mask register• READY: 0 for inserting wait states• HLDA: Signals that the μp has relinquished buses• DREQ3 – DREQ0: DMA request input for each channel• DB7-DB0: Data bus pins• IOR΄: Bidirectional pin used during programming and during a DMA write cycle• IOW΄: Bidirectional pin used during programming and during a DMA read cycle• EOP΄: End of process is a bidirectional signal used as input to terminate a DMA process or as output to
signal the end of the DMA transfer• A3-A0: Address pins for selecting internal registers• A7-A4: Outputs that provide part of the DMA transfer address• HRQ: DMA request output• DACK3-DACK0: DMA acknowledge for each channel.• AEN: Address enable signal• ADSTB: Address strobe• MEMR΄: Memory read output used in DMA read cycle• MEMW΄: Memory write output used in DMA write cycle
8237
8237/8257
Minimal System with a Minimal System with a DMA ControllerDMA Controller
RequestPeripheral
DeviceDMA
Controller
Memory
Acknowledge
CPU
On-Chip-BusInterrupt
BusArbiter
8237 DMA controller
Description of pin diagramD0-D7: it is a bidirectional ,tri
state ,Buffered ,Multiplexed data (D0-D7)and (A8-A15).
In the slave mode it is a bidirectional (Data is moving).
In the Master mode it is a unidirectional (Address is moving).
IOR: It is active
low ,tristate ,buffered ,Bidirectional lines. In the slave mode it function as a
input line. IOR signal is generated by microprocessor to read the contents 8257 registers.
In the master mode it function as a output line. IOR signal is generated by 8257 during write cycle
IOW: It is active
low ,tristate ,buffered ,Bidirectional control lines.
In the slave mode it function as a input line. IOR signal is generated by microprocessor to write the contents 8257 registers.
In the master mode it function as a output line. IOR signal is generated by 8257 during read cycle
CLK: It is the input line ,connected with TTL clock
generator. This signal is ignored in slave mode.
RESET: Used to clear mode set registers and status registers
A0-A3:These are the tristate, buffer, bidirectional address lines.
In slave mode ,these lines are used as address inputs lines and internally decoded to access the internal registers.
In master mode, these lines are used as address outputs lines,A0-A3 bits of memory address on the lines.
CS: It is active low, Chip select input line. In the slave mode, it is used to select
the chip. In the master mode, it is ignored.
A4-A7:These are the tristate, buffer, output address
lines.
In slave mode ,these lines are used as address input lines.
In master mode, these lines are used as address outputs lines,A0-A3 bits of memory address on the lines.
READY: It is a asynchronous input line. In master mode,When ready is high it receives the signal.When ready is low, it adds wait state
between S1 and S3 In slave mode , this signal is ignored.
HRQ: It is used to receiving the hold request
signal from the output device.
HLDA: It is acknowledgment signal from microprocessor.
MEMR: It is active low ,tristate ,Buffered control output
line. In slave mode, it is tristated. In master mode ,it activated during DMA read
cycle.
MEMW: It is active low ,tristate ,Buffered control input line. In slave mode, it is tristated. In master mode ,it activated during DMA write
cycle.
AEN (Address enable): It is a control output line. In master mode ,it is high In slave mode ,it is low Used it isolate the system
address ,data ,and control lines.
ADSTB: (Address Strobe) It is a control output line. Used to split data and address line. It is working in master mode only. In slave mode it is ignore.
TC (Terminal Count): It is a status of output line. It is activated in master mode only. It is high ,it selected the peripheral. It is low ,it free and looking for a new
peripheral.MARK: It is a modulo 128 MARK output line. It is activated in master mode only. It goes high ,after transferring every
128 bytes of data block.
DRQ0-DRQ3 (DMA Request): These are the asynchronous peripheral
request input signal. The request signals is generated by
external peripheral device.
DACK0-DACK3: These are the active low DMA acknowledge
output lines. Low level indicate that ,peripheral is selected
for giving the information (DMA cycle). In master mode it is used for chip select.
HLDA becomes active to indicate the processor has placed its buses at high-impedance state. as can be seen in the timing diagram, there
area few clock cycles between the time that HOLD changes and until HLDA changes
HLDA output is a signal to the requesting device that the processor has relinquished control of its memory and I/O space. one could call HOLD input a DMA
requestinput and HLDA output a DMA grant signal
25
8237 block diagram8237 block diagram
Description It containing Five main
Blocks.1.Data bus buffer2.Read/Control logic3.Control logic block4.Priority resolver5.DMA channels.
DATA BUS BUFFER: It contain tristate ,8 bit bi-directional buffer. Slave mode ,it transfer data
between microprocessor and internal data bus.
Master mode ,the outputs A8-A15 bits of memory address on data lines (Unidirectional).
READ/CONTROL LOGIC: It control all internal Read/Write operation. Slave mode ,it accepts address bits and
control signal from microprocessor. Master mode ,it generate address bits and
control signal.
Control logic block: It contains ,1. Control logic2. Mode set register and 3. Status Register.
CONTROL LOGIC: Master mode ,It control the sequence of
DMA operation during all DMA cycles. It generates address and control signals. It increments 16 bit address and decrement
14 bit counter registers. It activate a HRQ signal on DMA channel
Request. Slave ,mode it is disabled.
FIGURE FIGURE A DMA controller allows the peripheral to A DMA controller allows the peripheral to interface directly with memory without processor interface directly with memory without processor intervention. This allows the data transfer rate to approach intervention. This allows the data transfer rate to approach the access time of memory.the access time of memory.
Types:
Sequential DMA
Simultaneous DMA
FIGURE Three methods FIGURE Three methods (MODES)(MODES) of DMA of DMA operation: (a) byte; (b) burst; (c) block.operation: (a) byte; (b) burst; (c) block.
DMA is implemented using a DMA is implemented using a DMA controllerDMA controller
– DMA controller• Acts as slave to processor
• Receives instructions from processor
• Example: Reading from an I/O device– Processor gives details to the DMA controller
» I/O device number
» Main memory buffer address
» Number of bytes to transfer
» Direction of transfer (memory I/O device, or vice versa)
Processor initiates the DMA controller Gives device number, memory buffer pointer, …
Called channel initialization Once initialized, it is ready for data transfer
When ready, I/O device informs the DMA controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read, loops back to repeat the process
Notify the processor when done Typically uses an interrupt
Steps in a DMA operation
DMA controller details
Modes of OperationRotating priority Mode:
The priority of the channels has a circular sequence.
Fixed Priority Rotating Mode: The priority is fixed. TC Stop Mode Auto Load mode Extended Write mode
DMA Cycles1. DMA read2. DMA write 3. DMA Verify