A single rating inductor multilevel current source inverter with pwm strategie

International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 –

6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 4, July-August (2013), © IAEME

274

A SINGLE RATING INDUCTOR MULTILEVEL CURRENT SOURCE

INVERTER WITH PWM STRATEGIES AND FUZZY LOGIC CONTROL

B.Lakshmi.R

EEE Dept., Shri Vishnu Engg. College for Women,

Bhimavaram, AP, INDIA

ABSTRACT

In this paper a unique single rating inductor multilevel current source inverter (MCSI) is

explored taking advantage of the three different redundant zero states of the topology. The proposed

MCSI consists of identical modules in which the current flow is same in all the inductors. The

control and gate signal generation is achieved by Phase-Shifted Carrier SPWM with proper

implementation of a new state machine approach, which is easy to implement and allows both

current balance and minimized switching frequency with higher efficiency for industrial applications.

Space vector modulation is also implemented which will be an alternative for gate signal generation.

The performance of a seven level, three modules, arrangement is analyzed and is thoroughly

simulated with Matlab Simulink.

Keywords: fuzzy logic control, multilevel current-source inverter (MCSI), phase-shifted carrier

SPWM (PSC-SPWM), redundant zero states, space vector modulation.

I. INTRODUCTION

Multilevel voltage source converters have captured investigators attention and have been

used in major applications involving high power, while current source inverters have not been in

focus. Recent trends of electronic switches, which can rapidly turn on and off such as insulated gate

bipolar transistors (IGBT), emitter turn-off thyristors (ETO), [13] dual gate commutated thyristors

(Dual GCT), [12] integrated gate-thyristors (IGCT)], and low-losses SiC devices, has allowed

the implementation of sinusoidal pulse with modulation (SPWM) and space vector modulation

(SVPWM) techniques and multilevel schemes powered by a current source, ensuing low distortion

and fast dynamic response in high-power applications.

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Multilevel topologies present several advantages regarding total harmonic distortion and

stress on inductors and switches, Several Multilevel-CSI topologies have been developed.Multi-

rating-inductor-MCSI requires only two balance inductors for two adjacent modules, and every pair

of balance inductors carry different current values. There are no balance inductors in the paralleled

H-bridge-MCSI although the use of multiple independent dc current sources is necessary. In this

paper a single-rating-inductor-MCSI is employed to feed a three phase load. The converter

consists of a number of identical modules which determine the different current levels. Each

module uses two balance inductors and six power switches. All inductors of every module should

carry the same current values. The current flowing through the inductors can be balanced and

switching frequency can be reduced by applying a state machine modulation that properly uses

redundant zero states.

The selected topology has as many degrees of freedom to impose different current levels in

the three phases of the load as inductors acting as current sources. They are a smart choice to

improve performance and efficiency in industrial applications[14],where high power or low voltage

and high current are required, such as grid integration of renewable sources ,induction motor drives,

high-voltage direct-current (HVDC), flexible alternating current transmission system (FACTS).CSI

drives also have reliable short-circuit and overcurrent protection The current flowing through the

inductors can be balanced, and switching frequency can be reduced by applying a state-machine

modulation that properly uses redundant zero states. Industrial assembles are easy to develop and to

operate because all modules are identical[5].The behavior of this converter is very different from the

behavior of the traditional MVSI. Herein, each module carries a fraction of the load current, and

there is no separation of modules or switches per phase as occur in an MVSI. In this paper, the

SPWM logic has been modified for better performance and simple approach is presented showing

that current balance can be provided by adapting a well-known SPWM [5] and SVPWM as an

alternative strategy while minimizing switching speed using a novel sequential machine design.

In terms of power system control Multilevel concept offers new horizons, with the ability to

independently control the power system parameters like line active and reactive powers and bus

voltage. The multilevel concept also has the advantages like voltage capability, inductors current

continuity, decreased switching frequency and total harmonic distortion (THD) and thereby

decreasing switching losses. However, the increase in the use of the electronic switches due to the

increase in the output current levels demands an advanced control technique to the lower order

harmonics enhance the complex operation.

To mitigate the lower order harmonics Space Vector Pulse Width Modulation (SVPWM) is

an advanced modulation technique with optimized switching strategy. The most effective fuzzy logic

control is used to reduce the distortions in main source current where a PI controller is used

normally. In detail, this paper is organized as follows The circuit is brainy described in Section II-

A, followed by an analysis of the most important topics of the modulation method in Section II-B–D-

E. Section III presents the evaluation of the performance of the proposed inverter with simulation

results.

2. NOVEL CSI ARRANGEMENT

2.1. Switching Structure

The converter topology presented in Fig. 1, also known as “single-rating inductor MCSI”,

connected in parallel with the load and sharing a common current source consists of multiple CSI sub

circuits Each module consists of six switches and two inductors. In this inverter, each module

consists of two inductors and two inductors in series with the main current source splits the current in

equal shares from the main source which requires a very careful startup design. The main advantage

of this Multilevel CSI configuration is its modular structure, where each identical module handles



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only a fraction of the load current. The number of levels in output current can be determined

according to the number of modules “m” in

�� Where n=0, 1 ...2m (1)

Where m represents the number of modules and n goes from 0 to 2m. In this paper we consider

m=3 to obtain seven levels of load current

�� 1, �� , �� , 0, � �� , � �� , �1 (2)

Fig. 1: Basic MCSI scheme

The number of levels n in the output current can also be determined according to the number

of modules m in n = 2m+1, where m=1, 2, 3,....... .To obtain seven levels in the output current we

require 18 switches with bidirectional voltage blocking capability and six inductors i.e., two

inductors per module and two current sharing inductors in series with the main current source.

Distinguished load currents can be obtained by turning on and off each switch. An example of a valid

switch combination is shown in Fig. 2, and its corresponding switches states are presented in Table I.

In example 1, the switches A1, B1 and C1 are on, while a third of supply current “I“ is conducted by

each branch. Current into phase R equals “I”. The current in phase S is I/3 flowing from the load to

the source through switch A5 and the current on phase T is 2/3I flowing towards the source through

switches B6 and C6. The analysis of example 2 is analogous, providing 2/3I and 1/3I into phases R

and S respectively, while all current I flows outwards phase T. Solid lines in Fig. 3 show the current

paths through the whole converter down to the load for the examples described previously. By

changing more than one combination of switches each output current level can be generated .This

acts as an great advantage for MCSI compared to MVSI by minimising the switching frequency and

current control balance in the inductors of the converter which ultimately gives more degrees of

freedom than the traditional MVSI.

International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976

6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 4, July

Fig. 2: Current flow according to the switches in the on

TABLE 1: Switching combinations for examples in fig.2

2.2. SPWM of One Module SPWM Modulation is based on the comparison of a sinusoidal control signal with a triangular

carrier. Depending on the control signal whether it is greater or smaller than the carrier the

switches on each single branch are turned on or off. The standard three phase sine waves are given as

control signals for three phase loads. If SPWM is chosen

signals PR, PS, PT (Fig. 4b), generated can be used to turn on and off the switches in each leg of the

inverter by comparing one triangul

implement in CSI, in order to guarantee that the current of the module is imposed to a certain phase

of the load. The driving signals are obtained with some more manipulation of the signals to obtain

desired output current level, assuring current continuity in all th

PT two at a time (PR PS, PS PT, PT PR) is performed to identify which

levels and LR, LS, LT (Fig. 4c) are obtained. These signals indicate when each phase should deliver

current but they have no information of their polarity.


6553(Online) Volume 4, Issue 4, July-August (2013), © IAEME

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Current flow according to the switches in the on-state

Switching combinations for examples in fig.2

2.2. SPWM of One Module SPWM Modulation is based on the comparison of a sinusoidal control signal with a triangular

arrier. Depending on the control signal whether it is greater or smaller than the carrier the


control signals for three phase loads. If SPWM is chosen for voltage source inverters (VSI), the gate

b), generated can be used to turn on and off the switches in each leg of the

inverter by comparing one triangular with three sine waves (Fig. 4a).But this is not so easy to

CSI, in order to guarantee that the current of the module is imposed to a certain phase


desired output current level, assuring current continuity in all the inductors. First an XOR of PR, PS,

PT two at a time (PR PS, PS PT, PT PR) is performed to identify which of the branches have equal

c) are obtained. These signals indicate when each phase should deliver

ve no information of their polarity.


August (2013), © IAEME

SPWM Modulation is based on the comparison of a sinusoidal control signal with a triangular

arrier. Depending on the control signal whether it is greater or smaller than the carrier the


for voltage source inverters (VSI), the gate

b), generated can be used to turn on and off the switches in each leg of the

a).But this is not so easy to

CSI, in order to guarantee that the current of the module is imposed to a certain phase


e inductors. First an XOR of PR, PS,

of the branches have equal

c) are obtained. These signals indicate when each phase should deliver



Fig. 3: Current Flow



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Current Flow a)Example 1 b)Example 2

Fig.4: SPWM modulation





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Fig. 5: Gate Signal Logic Diagram

This means that signals Li combine both upper and lower switch signals in each branch (LR

A1 and A4, LS A2 and A5, LT A3 and A6). It is still necessary to identify whether the upper or the

lower switch should carry the current. This is performed with the help of signals Si (Fig. 4d) which

represent the polarity of the reference currents of each leg. Upper switch gate signal is obtained by

performing a logical AND of Li with Si. Lower switch gate signal is the logical AND of Li with

logical complement of Si [5]. The resulting six active states are shown in table II. Fig. 5 shows the

corresponding logic diagram. The combination of the valid conditions of all the switches form a set

of six active valid states that are shown in Table 2. Space vector modulation can be an alternative,

although it requires some higher computing efforts.

Table 2: Direct SPWM Gate Signals

2.3. Minimum Switching-Frequency Zero-State Selection Firing signals generated in Fig. 5e cannot directly drive IGBT’s gates since they generate

zero states by turning off all switches[1]. This does not allow inductor’s current continuity in a CSI,

e. g. time “z” in Fig. 4. Zero states generated by the SPWM logic should be recognized and replaced

by adequate zero states according to the CSI topology[7] as is developed in this section. A CSI

module can generate zero states in seven different ways as shown in Fig. 7 (where on switches are

highlighted). Closing all six switches (Fig. 6a) is the simplest implementation at the expense of

greater losses. The most efficient solution is closing only the two switches of a branch (Fig. 6b) in

terms of switching frequency. The worst case of combination of switches is shown in Fig. 6c, hence

it will not be considered. The identification of the six main sequences as shown in Fig. 8, e.g.

sequence A is a string of states 6, 2 and 0 in the form “…0 2 6 0 6 2 0 2 6 0 6 2 0…”is easy for

Performing a detailed analysis of the commutation signals (A1…A6) generated with SPWM (Fig.



280

5e) it is easy to identify six main Each active state (1 to 6) is generated as described in section II-B

and represents a combination of switches in a module according to table II. Each sequence (A to F) is

a state of the sequential machine displayed in Fig. 9. The jump from one sequence to the next is

performed by detecting a switching state that does not belong to the current sequence, e.g. sequence

B will run until a state 1 is generated by the PWM logic, then sequence C will be initiated. Correct

zero state implementation is mandatory when minimizing switching frequency, avoiding unnecessary

switches’ changes inside a sequence thus lowering power dissipation. Minimum switching frequency

can be accomplished by correctly choosing the zero state in each sequence. The table 3 shows that

only one zero combination is assigned to each sequence in order to minimize the switching

frequency. For example, during sequence B, turning on switches A1 and A4 as zero state avoids that

A1, A2 and A3 have to change state while the sequence is active. Logic state machine replaces zero

states generated by SPWM (all switches closed) by optimal zero combination according to the active

sequence. The active states are not affected by the state machine and pass through unchanged. Fig.

9 shows the gate signals of switch A1 as an example of the effect of the sequential machine on

commutation of the power switches. Gate signals generated with the state machine zero selection

(Fig. 9b) have much less commutations per cycle than all switches closed (Fig. 6a) zero approach

(Fig. 9a).

Fig. 6: Seven zero states possible for one CSI module

Fig. 7: Six Commutation Sequences



281

Fig. 8: Sequence of states

Table 3: Minimum switching frequency gate signals

Fig. 9: Gate signal for switch A1 a)SPWM b)sequential state machine



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2.4. Multilevel Operation: PSC-SPWM Multiple modules are arranged to produce a multilevel output current. Since load voltage

may affect the current balance over the sharing inductors a careful choice of the PWM should be

performed. The simplest way is to adopt a Phase-Shifted Carrier SPWM [3], [4].The PSC-SPWM

uses as many triangular carriers as modules have the converter. These carrier waves are delayed an

angle

Øk = ��k .where k=1,2,......m (3)

where m=3 and k goes from 1 to m as shown in Fig. 10

Fig. 10: PSC-SPWM modulation

The output current level is controlled by setting the reference sine waves amplitude. The

amplitude modulation index ma is then defined as,

m� � �� !��

2.5. Space vector pulse width modulation Every switching state can be represented as a vector in the converters α-β space vector plane.

The three phase currents can be transformed into two phase currents in α-β plane as represented

below.

"�#$%&�'$%&(= �� )1 � � � � � �0 √�� √��+ )�,-$%&�,.$%&�,/$%&+ (4)

A resulted space vector can be expressed as equation

I(t)= �#$%& 0 j�'$%& (5)

This can be rewritten as equation

i(t) =2�,-$%&e45 0 �,.$%&e46π7 0 �,/$%&e48π7 9 (6)

�,- = :�6 , �,.; � <� , �,/ � =�� (7)

Substituting the switching currents into equation (6), the resulted vector of switching state

can be driven. The resulted vectors are shown in a diagram which is called space vector diagram

shown in fig.12 since, the space vectors do not move, they are called stationary vectors. On the other



hand, the desired three-phase current on the AC side IW can be expressed as a reference vector

rotating counter clockwise in the vector plane. Each revolution of the reference

an entire fundamental cycle of the AC current. In other words, the reference current vector rotates at

the desired AC frequency. The ratio between the

can be synthesized by the adjacent

vector and the DC current determines the modulation index of the converter.

sequences are available but they are associated with different device switching frequencies and

harmonic profiles. The harmonic profile of the conventional SVM is undesirable for AC filter design

in the CSC. The AC capacitor together with the power supply side inductance or machine side

inductance will cause LC resonances. The resonance frequency is no

of the fundamental frequency to ensure not only desired current quality but also acceptable cost. The

low order harmonic currents, 5th and 7th orders in specific, will cause harmonic voltages as well as

resonance problems.

Fig. 11:

3. SIMULATION RESULTS

The proposed seven-level converter consists on three modules. Each switch is implemented

with an IGBT transistor and a series diode to allow bidirectional voltage bl

simple buck converter, with autonomous SPWM and a fuzzy logic control, provides the energy to the

main inductors.

The performance of the proposed converter is simulated with Matlab Simulink. The converter

arrangement is composed of three identical modules, each one built with six IGBTs with series

diodes. The sequential state machine for each module is implemented with Simulink’s state

tool. The output current of the simula

2/3I, 1/3I, 0, −1/3I, −2/3I, −I) can be recognized. A capacitor bank is used to filter the output current

The main parameters of the inverter is summarised i

regulated with a fuzzy logic control, acting on the firing angle of input rectifier’s thyristors. The

reverse power capability of the input rectifier allows four

of the load. The inverter output current is shown in Fig. 12a, where the seven leve

1/3I, -2/3I, -I) can be recognized. . A capacitor bank is used to filter the output current. The main

parameters of the inverter is summarised in the table IV.



283

phase current on the AC side IW can be expressed as a reference vector

rotating counter clockwise in the vector plane. Each revolution of the reference vector corresponds to


the desired AC frequency. The ratio between the magnitudes of the reference the reference vector

space vectors based on the principle of ampere

vector and the DC current determines the modulation index of the converter. Several switching


monic profiles. The harmonic profile of the conventional SVM is undesirable for AC filter design


inductance will cause LC resonances. The resonance frequency is normally between 3.5pu to 4.5 P.u



space vector diagram for 7-level CSI

level converter consists on three modules. Each switch is implemented

with an IGBT transistor and a series diode to allow bidirectional voltage blocking capabilities. A



mposed of three identical modules, each one built with six IGBTs with series

diodes. The sequential state machine for each module is implemented with Simulink’s state

tool. The output current of the simulated inverter is shown in Fig. 12(a), where the

I) can be recognized. A capacitor bank is used to filter the output current

rter is summarised in the table 4.The currents in main inductors are

trol, acting on the firing angle of input rectifier’s thyristors. The

reverse power capability of the input rectifier allows four-quadrant operation or regenerative braking

of the load. The inverter output current is shown in Fig. 12a, where the seven levels (I, 2/3I, 1/3I, 0,

. A capacitor bank is used to filter the output current. The main

parameters of the inverter is summarised in the table IV.



phase current on the AC side IW can be expressed as a reference vector

vector corresponds to


he reference vector

space vectors based on the principle of ampere-second balance

Several switching


monic profiles. The harmonic profile of the conventional SVM is undesirable for AC filter design


rmally between 3.5pu to 4.5 P.u



level converter consists on three modules. Each switch is implemented

ocking capabilities. A



mposed of three identical modules, each one built with six IGBTs with series

diodes. The sequential state machine for each module is implemented with Simulink’s state flow

(a), where the seven levels (I,

I) can be recognized. A capacitor bank is used to filter the output current.

n the table 4.The currents in main inductors are

trol, acting on the firing angle of input rectifier’s thyristors. The

quadrant operation or regenerative braking

ls (I, 2/3I, 1/3I, 0, -

. A capacitor bank is used to filter the output current. The main



284

Table 4: Inverter parameters

Figure 12: a) Inverter Output Current b) Load Current

Figure 13: Inductor Current Balance a)Inductor Current b)sharing inductor current

The output current is filtered to the load (Fig. 12b) with low distortion and Fig. 13 shows the

balance operation of all sharing inductors. It is clear that each inductor carries one third of the main

current. A detail of one of these currents is shown in Fig. 13b. The output current is regulated by

changing ma presenting a linear dependency. The current of the sharing inductors remains under

balance at different values of ma and the block diagram of the proposed MCSI is shown in fig.14.



285

Figure 14: Basic Block Diagram of the Proposed Inverter

4. CONCLUSION

A novel modular single rating inductor MCSI topology was analyzed in this paper. The

behavior of a seven level, three modules,with fuzzy logic control arrangement was simulated

showing excellent conditions of load regulation, linearity and dynamic response. As a result of

circuit topology and PSC-SPWM utilization, current balance was achieved in both main and sharing

inductors, even under load and operation point changes. The switching frequency was minimized

with a new state-machine approach, taking the advantage of the three different zero-states of the

topology.

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