Development of a Hybrid CVD / SOD Integration Sequence for Reliable, High Performance Interconnect Systems

J. Waeterloos1, S. Cummings1, Y. Ohmoto2, L. Archer3, R. Stevens4, S. Lucero1, K. Yang1, J. Im1, M. Mills1, R. Strittmatter1 , E. Beach1, S. Rozeveld1

1. The Dow Chemical Company, Advanced Electronic Materials, Midland MI USA2. Hitachi, Ltd. Kasado Administrative Division, 794, Higashitoyoi, Kudamatsu City,Yamaguchi Prefecture, 744-8601 Japan3. SEZ America Inc., 4829 S. 38th St. Phoenix, AZ 850404. ATMI, 617 River Oaks Pkwy., San Jose, CA 95134

(Email : jwaeterloos@dow.com )

Abstract

The use of hybrid integration schemes provides an option on how to increase the effects of CTE mismatch related the use of organic polymers as ILD. Sequential finite element analysis is used to determine the mechanics and subsequently a hybrid damascene interconnect is build to demonstrate the approach.

Key words

Porous SiLK, hybrid integration, damascene, etch, clean, parametric

INTRODUCTION

As device dimensions shrink, additional performance is required from the interconnect system. The two most commonly employed solutions are the use of copper to replace aluminum as the metal conductor and low dielectric constant materials (low-k) to replace silicon dioxide as the inter-level dielectric. The migration to copper has become a standard in the manufacturing of high-end products. The implementation and integration of low-k materials, however, is not as straightforward. In this work we will specifically focus on how low-k materials can be integrated to obtain a highly reliable system.

Motivation for using a Hybrid Integration Sequence

The proposed scheme is based on a so-called hybrid approach combining the best properties of two different materials: a SiOC CVD film at the via level and porous SiLK* semiconductor dielectric (*trademark of The Dow Chemical Company) at the trench level. Most low k CVD films have to compromise between fracture toughness and dielectric constant but retain coefficient-of-thermal-expansion (CTE)

values between 10 and 20 ppm/C. SiLK and porous SiLK films have lower k value, no frequency dispersion, and high fracture toughness but have a higher CTE value compared to SiOC films. Examples of Hybrid integration schemes has been shown by Toshiba/Sony in [1,2].

If a full SiLK stack is used, careful stack design is required as the higher CTE values of SiLK films can create additional mechanical stress in the via during thermal cycling events. Sequential finite element analysis (FEA) [3] has shown that the successful integration is not determined by just the interlayer dielectric (ILD) but is determined by the combination of materials used such as the type and thickness of the Cu capping film, stack height, via profiles, intrinsic stress of the metallization films, etc. An example of a FEA analysis of a dual damascene structure is shown in Fig. 1.

Fig.1 : FEA analysis of a full SiLK dual damascene stack. Due to the CTE mismatch an increases stress is observed at the via.

A via however can be considered as a local 3-dimensional structure and is typically the most sensitive to CTE related stress. To alleviate this aspect of the integration reliability, a compromise is made. A material with a higher k value but with a lower CTE is used at the via

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y (MPa)

level. A trench can be viewed as a 2-dimension structure and is therefore much less sensitive to CTE mismatch and related stress. It is also at that level that the interline capacitance exerts the highest influence and the lowest k value would be desired.

Integration process sequence

For hybrid several integration approaches can be explored. In principle, a trench-first or via-first approach could be selected. Both options have intrinsic advantages and disadvantages. When misalignment of one level to the other would occur, the trench-first approach has the advantage that the via barrel size does not change with the degree of lithographic misalignment however the metal spacing does. In the case of a via-first approach, the metal spacing not altered but there is a direct impact on the metal to via overlap. A brief overview of the integration sequence is shown in Fig. 2.

Fig 2 : (left) Dual damascene via first approach ; (right) Single damascene viafirst approach

A statistical RMS analysis incorporating shows that a via-first approach is preferred as the highest design rule accuracy can be obtained. The root cause is that for a via-first sequence the via(n) is aligned to metal(n) and metal (n+1) is aligned to via(n). In the case of a trench-first scheme both via(n) and metal (n+1) are aligned to metal(n).

A second degree of freedom is to be found in whether a single or dual damascene approach is used. Both options are explored and results will be presented in the next sections. It however needs few comments that a dual damascene approach will have a lower cost-of-ownership (CoO) compared to a single damascene sequence.

If a dual damascene is pursued, a third choice needs to be made whether to etch the via in the SiOC and then apply the porous SiLK film or the deposited the entire stack, i.e SiOC and porous SiLK film, followed by the patterning sequence. The impact is that the material performance criteria and required patterning development/performance is impacted by this choice. In this work, the via was etched in the SiOC film before deposition in the SiLK film. A more detailed discussion can be found in [4].

Process modules

The processing of the wafers was completed at different sites. All processing was done using the wafer service division of ISMT with the exception of coat and cure being performed in Dow’s Application Lab ; etch was done HHT, Post etch clean was done using ATMI chemistry on a SEZ tool. All formerly mentioned companies are members of the SiLKNet Alliance.

Coat/cure

A 250 nm porous SiLK Y film was spin coated on the substrate using a TEL SOD ACT8 in Dow’s Auburn facility. Subsequent to the hotplate bake under N2, a 2 hour, 400C furnace cure was given using an Eaton Compact II furnace. Typical uniformities which are obtained are below 0.3% 1 sigma. Porous SiLK Y has an average pore size smaller than 2nm obtained by creating subtractive porosity. With porous dielectrics the barrier continuity is always of great concern. The properties in general and specifically the barrier continuity is discussed in [5]

Patterning

The lithography was done using 248 nm lithography with a 200 nm line space target. A 60 nm BARC was used to suppress an substrate reflectivity issues. For both integration schemes the via- first sequence was used.

In both cases of the single damascene or dual damascene process sequence as show in Fig. 2, the via patterning is fairly straightforward. In the case of the SD strategy the metallized via is capped with a SiC film which will act as a stopping layer for the trench etch. It is however for the dual damascene scheme that the patterning is much more difficult.

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All dielectric etches are done on a UHF-ECR Plasma Etching System U-622, which enables a stable discharge is provided in low-pressure/middle-density plasma region UHF-ECR system. The hardmask opening is again a well know process step. The challenge is found in etching the p SiLK film as much as possible before the resist is fully consumed. The latter will result in the onset of CD gain. The second issue related to profile control. The p SiLK inside the plug needs to be removed during the etch step. During this event the p SiLK at the sidewalls will be exposed to the etch chemistry for a prolonged time and lateral etching may occur. As is seen in Fig. 3, good profile control can be obtained by using adequate process conditions.

Fig 3 : Trench patterning in the case of the single damascene approach where hardmask, p SiLK film and SiC are opened

The final step is the Cu cap opening step. Although seemly a trivial step, due to the selectivity of the Cu cap to other films, quite some hardmask is removed. This loss of hardmask needs to be accounted for when establishing the required. hardmask thickness

Post etch clean

The post dry strip residue removal step was achieved by processing the wafers on an SEZ Single Wafer Spin Processor using ATMI’s PT-15 residue removal chemistry at the SEZ America process lab. The Spin Processor utilizes a Bernoulli chuck and Bernoulli edge-contact-only (ECO) handling system to minimize handling and defect exposure. PT-15 is a semi-aqueous fluoride-based chemistry typically used in post etch residue removal for dual damascene, copper/low K device manufacturing and was developed particularly for use in single wafer spray tool applications such as the SEZ platform. The baseline Process-of-Record (POR) was determined using DOE procedures and examination of the

resultant degree of cleanliness using SEM analysis. The eventual process chosen was 60 sec. at 25 °C. Representative SEM images are shown in Figures 4 and 5. PT-15 shows good compatibility with porous SiLK and is not deleterious to the exposed Cu metal.

Fig 4 : Dual Damascene trench structure prior to wet cleaning. The filled via is clearly visible to the left of the image.

Fig 5 : Dual Damascene Trench structure after exposure to PT-15 at 25 °C for 60 sec..

Metallization

A Ta based PVD barrier is used as Cu barrier followed by the seed deposition. Trench CU fill is performed using electrochemical plating. Once the plating is completed the excess Cu is removed by chemical mechanical polishing using a two step polishing process dedicated to Cu and subsequent barrier removal.

Parametric evaluation

A key parametric figure of merit is found in interline leakage current. Since different etch chemistries are used the pattern the low k films and barriers, the low k films are exposed to these chemistries in sequence. In Fig. 6 the interline leakage current is shown measured using a finger-comb structure having 0.225 um line/space. As is seen the leakage current is

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low indicative that no first order film damage has occurred.

Fig. 6 : M2 interline leakage current

In Fig 7 the M1-M2 via resistance for a 336k via chain. The via dimension is targeted at 0.225um. The resistance is plotted as the resistance per via.

Fig. 7 : Via chain resistance

Performance evaluation

The key question is whether the process yield benefit of using a hybrid still gives the performance required according to the system design specs. The key driver being the interline capacitance which is becoming a dominant part in the device loading capacitance. Due to the extremely small geometries being used, fringing electrical fields impact the total interline capacitance as much as the parallel plate component. Since these fringing field go through the hardmasks and SiOC film at the via level, higher effective values are obtained compared to when a full p SiLK stack would be used, yet the obtained values are low enough to typically meet requirements. An overview is given in Fig.8. A hidden advantage to such a scheme is that the k value can actually be tailored to fit the needs and thus increase the robustness of the technology under development by using fewer

novel materials or to use this in combination with SiO2 based materials. AS can be seen a very large impact is found when changing in the hardmask films from Si3N4 (k=8) to SiC (k=4.5) [7].

Fig. 8 : Impact on k effective when using different types of dielectrics at via/trench level [7]

Conclusion

In conclusion it is clear that the hybrid approach does offer specific benefits related to process window breadth and reliability aspects. The penalty for this may be a slightly higher overall effective dielectric constant and a few more process steps than are employed in an architecture consisting of only one dielectric material.

Acknowledgement

The authors would like to thank the Dow Auburn Application group and the Porous SiLK development group. The SiLKNet Alliance (SM) is also acknowledged for supporting the activity. Special thanks go to Brent Ames and Frank Tolic from ISMT Wafers services.

References[1] A. Kajata et al, Proceeding of the IITC 2003, San Francisco, CA[2] R. Kanamura et al, Symp. VLSI Techn. Digest of Techn. Papers 2003, Kyoto Japan[3] K. Yang et al, Mat. Res. Soc. Symp. Proc. Vol. 766[4] J. Waeterloos, “Integration of SiLK Semiconductor Dielectric”, Chpt 10 in Low dielectric constant materials for IC applications, Ed P. Ho, J. Leu, W. Lee, Springer-Verlag, ISBN 3-540-678190[5] R. Strittmatter et al, Proc. Of the AMC, Montreal 2003, in press[6] L. Archer et al., Fall ECS Conference, Orlando FL., Oct 2003, in press[7[ D. De Roest et al, MAM 2001 proceedings

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