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INTRODUCTION • The regulations regarding electromagnetic
compatibility (EMC) can affect many aspects of circuit and system design. However, there are many considerations that can be applied generally to reduce both the emissions from and susceptibility to electromagnetic interference (EMI).
• Our design should be capable of minimizing emissions and committed to achieve EMC compliance by correct component choice and design. For this every design shall be complied with the list of general design considerations .
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EMC FUNDAMENTALS
The coupling path is frequency dependent
High frequencies are radiated
Low frequencies are conducted
The boundary is typically about 30 MHz
There are 5 aspects to EMC when finding the problem
Frequency - Where in the spectrum is the problem observed?
Amplitude - How strong is the energy source?
Time - Is it continuous or intermittent with operation?
Impedance - What is the Z of the source and receiver?
Dimensions - What are the physical dimensions of the device which will allow emissions? (RF currents will leave through openings which are fractions of a wavelength!)
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How PCB’s Radiate RF Energy
• Digital signals with fast rise/fall times contain
very high frequency components even for low
clock frequencies! Fmax = 1/π tr
• The RF currents from the switching choose the
low impedance path
• The Z0 of air is about 377Ω
• Discontinuities in the RF return path ZRF>> 377Ω.
• RF current leaves the board in favor of the air =
EMI
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GROUND SYSTEM
• Low inductance ground System, Maximizing ground plane reduces inductance and capacitance reduces EM emission and Cross talk. Distributed ground system reduces return currents.
• The ground connections should be laid out as a ground plane to avoid generating stray inductance that can negate the effect of the capacitors, or worse, generate a resonant circuit that can lead to parasitic oscillations.
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POWER SUPPLY CONSIDERATIONS
• Eliminate loops in supply
lines (see figure ).
• Decouple supply lines at
local boundaries (use RCL
filters with low Q, see
figure ).
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POWER SUPPLY CONSIDERATIONS
• Place high speed sections close to the power line input, slowest section furthest away (reduces power plane transients, see Figure
• Isolate individual systems where possible (especially analogue and digital systems) on both power supply and signal lines (see figure ).
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SIGNAL LINE CONSIDERATIONS
• Use low pass High pass and band pass filters wherever applicable to limit the band width to optimum.
• Keep feed and return loops close on wide bandwidth signal lines.
• Terminate lines carrying HF or RF signals correctly (this minimizes reflection, ringing and overshoot, see figure ).
• Terminate lines carrying signals external to a board at the board edge, avoid lead terminations within the board and loose leads crossing the board.
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SIGNAL LINE CONSIDERATIONS
• Track all signals on the
board, avoid flyi g leads a ross the oard.
• Minimize rise and fall
times on signal and
clock edges (sharp
edges produce wide hf
spectra), slew rate
limiting also reduces
crosstalk (see figure ).
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PCB CONSIDERATIONS • Avoid slit apertures in PCB layout,
particularly in ground planes or near current paths.
• Areas of high impedance give rise to high EMI, use wide tracks for power lines on the trace side.
• Make signal tracks strip line and include a ground plane and power plane whenever possible.
• Keep HF and RF tracks as short as possible, lay out the HF tracks first (see figure ).
• Avoid track stubs, these cause reflection and harmonics (see figure).
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PCB CONSIDERATIONS • On sensitive components and
terminations use surrounding guard ring and ground fill where possible (see figure ).
• A guard ring around trace layers reduces emission out of the board, only connect to ground at single point and make no other use of the guard ring (i.e. do not use to carry ground return from a circuit).
• A guard ring around trace layers reduces emission out of the board, only connect to ground at single point and make no other use of the guard ring (i.e. do not use to carry ground return from a circuit).
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PCB CONSIDERATIONS
• Avoid overlapping power planes, keep separate over common ground (reduces system noise and power coupling, see figure ).
• Power plane conductivity should be high, therefore avoid localized concentrations of via and through hole pads (surface mount is the preferred assembly technology)
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PCB CONSIDERATIONS
• Track mitring (bevelling the edges at corners) reduces field concentration (see figure ).
• If possible make tracking run orthogonally between adjacent layers (see figure ).
• Do not loop tracks, even between layers, this forms a receiving or radiating antenna.
• Do not leave any floating conductor areas, these act as EMI radiators, if possible connect to ground plane (often these sections are placed for thermal dissipation, hence polarity should be unimportant but check component data sheet, see figure).
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PCB CONSIDERATIONS
Board Layers
• Care must be taken that the ground layer should
always be between high-frequency signal traces
and the power plane. If a two-layer board is used
and a complete layer of ground is not possible,
then ground grids should be used. If a separate
power plane is not used, then ground traces should
run in parallel with power traces to keep the supply
clean.
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COMPONENT CONSIDERATIONS • Locate biasing and pull up/down
components close to driver/bias points.
• Minimize output drive from clock circuits.
• Use common mode chokes between current carrying and signal lines to increase coupling and cancel stray fields (see figure 14).
• Decouple close to chip supply lines, reduces component noise and power line transients (see figure 15).
• Use low impedance capacitors for decoupling and bypassing (ceramic multilayer types are preferred due to high resonant frequency and stability).
• Use discrete components for filters where possible (surface mount is preferable due to lower parasitic and aerial effects of terminations on through hole parts).
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COMPONENT CONSIDERATIONS • Ensure filtering of cables and over voltage protection at the
terminations (this is especially true of cabling that is external to the system, if possible all external cabling should be isolated at the equipment boundary).
• Minimize capacitive loading on digital output by minimizing fan-out, especially on CMOS ICs (this reduces current loading and surge per IC).
• If available, use shielding on fast switching circuits, mains power supply components and low power circuitry (shielding is expensive a d should e a last resort optio ).
• In general, keeping the bandwidth of all parts of the system to a minimum and isolating circuits where possible reduces susceptibility and emissions. Considerations which are applicable to reducing noise levels are equally applicable to EMC compliance, EMC compliant circuits should obviously exhibit low noise levels.
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COMPONENT CONSIDERATIONS • Connectors should be placed on side or corner of the board-Locating the
connectors on one edge of the board makes it much easier to hold them all to the same reference potential. This is extremely important for boards with high-frequency components that will not be housed in a shielded enclosure. Some designs require that connectors be located on different sides of the board. In these cases, every effort should be made to avoid placing high-frequency circuits between any two connectors. When placing high-frequency circuits between connectors is unavoidable, a metal enclosure and filtering to chassis ground is generally necessary to keep the board from being able to drive common-mode currents on to the attached cables.
• A device on the board that communicates with a device off the board through a connector should be located as close as possible (e.g. within 2 cm) to that connector.
• All off-board communication from a single device should be routed through the same connector.
• Components not connected to an I/O net should be located at least 2 cm away from I/O nets and connectors.
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COMPONENT SELECTION
Isolated DC-DC Converters
• An isolated DC-DC converter can provide a significant benefit to reducing susceptibility and conducted emission due to isolating both power rail and ground from the system supply. Isolated DC-DC converters are switching devices and as such have a characteristic switching frequency which may need some additional care and filtering.
Segregation of components
• Components need to be segregated with functionality – Analog, Digital, high speed digital, RF and so on. The tracks for each group should stay in their designated area. For a signal to flow from one subsystem to another, a filter should be used at subsystem boundaries
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RF Sources for EMI/EMC
• Noise in Micro computer Chips- traces acts as antenna
• I/O Pins of digital ICs- traces acts as antenna
• Power Supply: Switching harmonics. Traces
• Oscillator circuits:
• Loops and Dipoles: Loops and dipoles are antennas. Their radiating efficiency increases up to 1/4 wavelength (l) of the frequency of interest. Geometrically, that means, in the case of a loop, that the larger the laid-out area of the loop, the stronger the radiation until one or both legs of the loop reach 1/4 wavelength. In the dipole, the longer the antenna, the more radiation, until the length of the antenna reaches 1/4 wavelength. At 1 MHz, 1/4 l = 75 m. At 300 MHz, 1/4 l = 25 cm, or about 10 inches.
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GENERAL Digital Circuits
• When dealing with digital circuits, extra attention must be given to clocks and other high speed signals. Traces connecting such signals should be kept as short as possible and be adjacent to the ground plane to keep radiation and crosstalk under control. With such signals, engineers should avoid using Vias or routing traces on the PCB edge or near connectors. These signals must also be kept away from the power plane since they are capable of inducing noise on the power plane as well. While routing traces for an oscillator, apart from ground no other trace should run in parallel or below the oscillator or its traces. The crystal should also be kept close to the appropriate chips.
Clock Termination
• Traces carrying clock signals from a source to a device must have matching terminations because whenever there is an impedance mismatch, a part of the signal gets reflected. If proper care is not provided to handle this reflected signal, large amount of energy will be radiated. There are multiple forms of effective termination, including source termination, end termination, AC termination, etc.
Analogue Circuits
• Traces carrying analog signals should be kept away from high-speed or switching signals and must always be guarded with a ground signal. A low pass filter should always be used to get rid of high-frequency noise coupled from surrounding analog traces. In addition, it is important that the ground plane of analog and digital subsystems not be shared.
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GENERAL
Decoupling
• Any noise on the power supply tends to alter the functionality of a device under operation. Generally, noise coupled on the power supply is of a high frequency, thus a bypass capacitor or decoupling capacitor is required to filter out this noise.
Cables
• Most EMC-related problems are caused by cables carrying digital signals that effectively act as an efficient antenna. Ideally, the current entering a cable leaves it at the other end. In reality, parasitic capacitance and inductance emit radiation. Using a twisted pair cable helps keep coupling to a low level by cancelling any induced magnetic fields. When a ribbon cable is used, multiple ground return paths must be provided. For high-frequency signals, shielded cable must be used where the shielding is connected to ground both at the beginning and at the end of the cable.
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GENERAL • Shielding: Shielding is not an electrical solution but a
mechanical approach to reducing EMC. Metallic packages
(conductive and/or magnetic materials) are used to prevent
EMI from escaping the system. A shield may be used either to
cover the whole system or a part of it, depending upon the
requirements. A shield is like a closed conductive container
connected to ground which effectively reduces the size of
loop antennas by absorbing and reflecting a part of their
radiation. In this way, a shield also acts as a partition
between two regions of space by attenuating the radiated
EM energy from one region to another. A shield reduces the
EMI by attenuating both the E-Field and H-field component
of radiating wave.
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GENERAL • Connectors should be located on one edge or on one
corner of a board.
• A device on the board that communicates with a device off the board through a connector should be located as close as possible (e.g. within 2 cm) to that connector
• All off-board communication from a single device should be routed through the same connector.
• Components not connected to an I/O net should be located at least 2 cm away from I/O nets and connectors.
• Don’t lo ate ir uitry etween connectors
• Minimize signal current loop areas.
• Avoid sharp corners in traces
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EMI SUPPRESSION
• Image Planes
• � The 20-H Rule
• � System Level Grounding
• � Partitioning
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EMI SUPPRESSION
• Image Planes
An image plane is a layer of copper (either a voltage or a ground plane) which physically adjacent to the signal routing plane. The image plane provides a low impedance path for the RF currents and reduces the EMI emissions since the RF currents use the plane instead of the air
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EMI SUPPRESSION
Image Plane Violations
Routing traces in the image plane will create slots in
the RF return path and create a large loop area and
potential EMI!!
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EMI SUPPRESSION The 20-H Rule
• RF currents fringing between the power and ground planes at the edge of the board can result in RF emissions.
• � Reducing the size of the power plane with respect to the ground plane will reduce these emissions.
• � This increases the intrinsic self-resonant frequency of the PCB.
• � The ground plane should exceed the power plane by 20�H where H is the total thickness between the power and ground planes
• � 20-H provides for approximately a 70% reduction of the fringing flux and changing to 100-H will provide about a 98% reduction.
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EMI SUPPRESSION � System Level Grounding
There are three main system grounding methods
Single-Point Grounding
Either Series or Parallel
Best for frequencies below 1 MHz
Has the largest amount of ground loop currents
� Multi-point Grounding
Preferred for frequencies above 1 MHz.
Minimizes loop currents and ground impedance of planes.
Lead Lengths must be kept extremely short
Provides for maximum EMI suppression at the PCB level
Hybrid : A mixture of both Single-Point and Multi-Point Grounding in the same system.
� Ground loops cause RF energy to be radiated when high inductance returns are provided.
� Note: Do not count on mounting screws to provide low inductance connections. They are highly inductive and can act as helical antennae at high frequencies (100 MHz-1 GHz)!! (Use conductive gaskets in addition to the screws.)
� In a Multi-point ground system, the distance between the screws should not exceed λ/20 of the highest edge rate on the PCB.
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EMI SUPPRESSION
� Partitioning
Portioning consists of breaking a board up into functional
areas with respect to the bandwidth of the functional
block.
Grounding connections are made around the perimeter of
each functional block using spring finger, screws, gaskets,
etc, provided that the method has a sufficiently low
inductance between the ground plane and the chassis
ground.
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SIGNAL INTEGRITY
• Ringing and Reflection
• � Cross-Talk
• � Power and Ground Bounce
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SIGNAL INTEGRITY
Ringing and Reflection�
Transmission line properties which occur between the source and load. Possible causes:
• � Changes in trace width
• � Improperly matched termination networks
• � Lack of terminations
• � T-stubs, branched or bifurcated traces
• � Varying loads and logic families
• � Large power plane discontinuities
• � Connector transitions
• � Changes in trace impedance
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SIGNAL INTEGRITY
Signal Distortion:
• Ringing is minimized by proper terminations (e.g. series R)
• � Rounding means the net is over damped. Do t forget about the shunt capacitance of the trace as well as the load
capacitance.
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SIGNAL INTEGRITY
Cross-Talk
• cross-talk requires a 3-wire circuit!
• �Terminating resistors with a common pin susceptible!
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SIGNAL INTEGRITY Preventing Cross-Talk : First, note the following observations:
• � Decreasing the trace separation increases the mutual capacitance Cm and the cross-talk.
• � With parallel traces, longer parallel lengths increase the mutual inductance Lm and the cross-talk.
• � Decreasing the rise time of the signal, increases the cross-talk.
Some Solutions are:
1. Group and locate logic devices according to functionality.
2. Minimize routed distance between components
3. Minimize parallel routed trace lengths
4. Locate components away from I/O interconnects and other areas susceptible to data corruption.
5. Provide proper terminations on impedance controlled traces or routed traces rich in harmonic energy
6. Avoid routing traces parallel to each other. Provide sufficient separation between traces to minimize inductive coupling (The 3 W Rule) or use guard traces.
7. Route adjacent signal layers orthogonal to reduce capacitive coupling between the layers.
8. Reduce signal-to-ground reference distance separation.
9. Reduce trace impedance and/or signal drive level
10. Isolate signal layers which must be routed in the same axis with a solid planar structure
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SIGNAL INTEGRITY Cross-Talk : The 3-W Rule
• This rule for trace separation will reduce the cross-talk flux by approximately 70%. (For a 98% reduction, change the 3 to 10.)
• The distance of separation between traces must be three times the width of the traces, measured center-line to center-line.
Note that the traces near the edge of the plane need to be > 1W from the edge!
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SIGNAL INTEGRITY Cross-Talk : Guard/Shunt Traces
Guard traces surround the high-threat traces (clocks, periodic signals, differential pairs, etc.) and are connected to the ground plane. They are very useful in 2-layer boards.
The guard trace should be smallest, tolerable manufacturable spacing from the signal.
The guard trace is connected to ground.
If a ground plane is available, make ground connections no farther than λ/20 apart.
Shunt traces are traces located immediately above a high-threat trace and follow the trace along the entire route. They are best used in multi-layer (6 or more) boards
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SIGNAL INTEGRITY Power and Ground Bounce:
• Ground bounce is caused by the simultaneous switching of drivers in an IC package and may cause functionality as well as EMI concerns. Ground bounce presents a situation where the ground reference system is not at a constant 0 V reference value.
•� Be sure to provide a separate ground connection for each ground pin directly to the ground plane. Connecting two ground terminals together with a trace to a single via defeats the purpose of having independent ground leads on the device package!
•� Also, choose component packaging carefully: use devices with a ground reference in the center of the device to reduce the Lgnd (4nH vs 15nH). Surface mount devices are preferred over through-hole packages for this reason.
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BYPASSING AND DECOUPLING
• Capacitor Usage and Resonance
• � Parallel Capacitors
• � Placement
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BYPASSING AND DECOUPLING � Types of capacitor usage
There are three primary uses for capacitors:
1. Bulk Used to maintain constant DC voltage and currents when all signal pins switch. Also prevents power drop out due to dI=dt current surges from the components.
2. Bypassing Removes unwanted common-mode RF noise from components or cables by placing an AC-short to ground. This keeps the unwanted energy from entering a protected area as well as limiting the bandwidth. Bypassing is also used to divert RF energy from one area to another.
3. Decoupling Removes RF energy injected into the power planes from high frequency components o su i g po er at the de i e s s it hi g speed. They also provide a small amount of energy to function as localized bulk capacitors.
Remember, the capacitors really have an ESL and ESR.
Through-hole: ESL.35nH and ESR.50mΩ.
Surface Mount: ESL.1nH and ESR.5m Ω.
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BYPASSING AND DECOUPLING Tips on Paralleling Capacitors :
Parallel capacitors of the same value will increase the net capacitance and reduce the ESL and ESR. The reduction of the ESL and ESR is the most important property. Improvements of 6dB have been observed (replacing one capacitor with multiple smaller ones).
•� Be careful to remember that the values will be different and anti-resonance will occur.
•� Choose values such that the anti-resonance will not occur at a harmonic of a generated signal (either a switching or transition frequency).
•� See Printed Circuit Board Design Techniques for EMC Compliance, for capacitor value design procedure.
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BYE PASSING AND DECOUPLING
Capacitor Placement:
• Key idea is to reduce path inductance � location
• � The location of the components is limited by
mechanical constraints
• � SMT parts can be closer than THT parts
• � Trace inductance will be 3-10x larger than plane
inductance
• � Each via adds 1-3 nH of inductance
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