M Traxler TRB and Trasgo

Michael Traxler, GSI 12010-02-05

TRB: A platform for TDC and digital TRB: A platform for TDC and digital readoutreadout

OutlineOutline

• Motivation for TRB• Implementation of the idea• Measurements and results• New developments• Local computing capability: my point of view• Summary


Motivation for TRBMotivation for TRB

Given Task:Given Task: TDCs + fast DAQ for 2244 channels tRPC

• Big project, many people involved => huge effort• TDCs are used everywhere in nuclear physics

experiments• A general solution is wanted, which can be reused

for other detectors and different experiments– Not only for TDCs, but also for other tasks

• HADES: around 80k channels, 100kHz event rate, 250MBytes/s sustained data rate for Au+Au

• Other issue: price and development time


Concept for HADES DAQ: TRBConcept for HADES DAQ: TRB

• One platform for all tasks• Directly mounted on the detector

– no long cables• Integrated DAQ• Includes local power-supplies• Modular design

– Pluggable AddOns to TRB• High granularity (~70 TRBs)• Dedicated network protocol (TRBnet)• Reduces development effort/time and simplifies the

debugging process

Publication:„A General Purpose Trigger and Readout Board for HADES and FAIR-Experiments“I. Fröhlich et al., Nuclear Science, IEEE Transactions on,Volume 55, Issue 1, Feb. 2008 Page(s):59 - 66


The TRBv2The TRBv2

DC/DCDC/DCETRAXETRAX

DSPDSP

FPGAFPGAVirtex4Virtex4

TDCTDC0, 10, 1

TDC 2, 3TDC 2, 3

SDRAMSDRAM Optical linkOptical link

SDRAMSDRAM

EthernetEthernet

4 TDCs – 128 channels

FPGA – Virtex4LX404x512Mb SDRAMETRAX FS – 4 processors, Linux

100Mb/s,TCP/IP2,5 Gb/s optical linkDSP TigerSharcAddOn connector48V isolated DC/DC converters


Results of TRB developmentResults of TRB development

Time resolution:Time resolution:• 128 channels: ~40ps RMS• 32 channels: ~16ps RMS

Field of Usage:Field of Usage:• Successfully used in many production beam times in HADES• Platform for: TDC (RPC + discriminator and charge measurement for

PMTs), ADC and pure digital readout (everything)• Used not only by HADES:

– PANDA - DIRC detector (in beam in 2009), PANDA - MDC readout– CBM – MAPS detector development – PET- scanner prototype in Coimbra– KVI - development of FPGA algorithms – HPLUS - in China, Lanzhou Institute– And many more planned applications


New developments / future plansNew developments / future plans

• Better time resolution– Replace HPTDCs

• Reduce costs– More cost sensitive FPGA– Remove DSP

• Needed tasks:– Replace the obsolete components– 1 GbE Ethernet with Linux-CPU


TDC implemented in FPGATDC implemented in FPGA

• A Tapped Delay Line (carry chain) TDC has been implemented in a FPGA (Virtex 4) (asynchronous design)– Time resolution: <10ps– 32 channels in one FPGA– Very promising results!

• To Do:– Implement all features of HPTDC in the FPGA (e.g.

window matching)– Implementation of design in cost sensitive FPGAs

(Lattice ECP2M, Altera Arria GX, etc.) and evaluate performance


TDC in FPGA: resultsTDC in FPGA: results


Local ComputingLocal Computing

• Potential is very high– FPGA + DSP

• Realization is really hard– DSP has been abandoned (no manpower)– FPGA does data transfer/sorting/zero

suppression/networking/switching (RTL)– KVI: Peak detection with baseline restoration (RTL)– All: Several man year projects

• Going beyond the mentioned is very ambitious– Runge-Kutta for tracking + other complex algorithm– Special hardware algorithms double the work; should be

very similar for off- and online analysis• Parallel calculation on GPUs seems to me the way to go

– Very promising results for Runge-Kutta


Local Computing IILocal Computing II

• Concept in many experiments– Digitize at the detector, the closer the better– Apply simple algorithms to reduce data amount– Transport the data (data transport is relatively cheap)– Local computing is expensive and is producing heat!– Commercial general purpose computing (e.g. GPUs) is

not beatable, except for special applications


SummarySummary

• A very successful platform for many channels TDC + DAQ has been built, useful for many applications

• In the future we can adapt much better to the users need by using FPGAs as TDCs: the compromise out of channels (price) and time resolution can be changed by programming

• Local computing resources (FPGA) are available• Costs will be reduced


Involved People in TRB designInvolved People in TRB design

E. Bayer1, M. Böhmer5, I. Fröhlich4, J. Michel4,M. Kajetanowicz3, K. Korcyl2, G. Korcyl2, M. Palka1,2 ,

P. Salabura2, P. Skott1, M. Traxler1, R. Trebacz2, S. Yurevich1

1 GSI, Darmstadt, Germany, 2 Jagiellonian University, Krakow, Poland,

3 Nowoczesna Elektronika, Krakow, Poland,4 J.-W. Goethe-Universitaet, Frankfurt, Germany,

5 Technische Universität, München, Germany


TRBTRB

Thank you for your attention!


CTS

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RPC

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Parallel Parallel Event BuildingEvent Building

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System OverviewSystem OverviewT

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M Traxler TRB and Trasgo