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MDE based FPGA physical Design Fast prototyping with Smalltalk Ciprian Teodorov, Loïc Lagadec [email protected] Lab-STICC MOCS UMR 3192

MDE based FPGA physical Design Fast prototyping with Smalltalk

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Page 1: MDE based FPGA physical Design Fast prototyping with Smalltalk

MDE based FPGA physical Design Fast prototyping with Smalltalk

Ciprian Teodorov, Loïc Lagadec [email protected] Lab-STICC MOCS UMR 3192

Page 2: MDE based FPGA physical Design Fast prototyping with Smalltalk

FPGAs

Compute node

Programmable interconnection

I1+i2 i1

i2

LUT LUT

LUT

LUT LUT LUT

LUT

i1

i2 I1-i2

LUT

LUT E/S

µP

“Flexible” hardware Time to market

Hard to program Hard to debug

Page 3: MDE based FPGA physical Design Fast prototyping with Smalltalk

FPGAs “Flexible” hardware Time to market

Hard to program Hard to debug

EDA required !

• C to circuit

• Debug

• Benchmarking

Page 4: MDE based FPGA physical Design Fast prototyping with Smalltalk

Our Smalltalk-based EDA legacy

Page 5: MDE based FPGA physical Design Fast prototyping with Smalltalk

Legacy backfires

"   Early developments (MADEO) started in 1996

"   Fast evolving domain (Moore + Murfy)

"   Refactoring is not enough to keep in the race

"   We have to re-design our framework

Page 6: MDE based FPGA physical Design Fast prototyping with Smalltalk

New direction

"   We need to shift from "   a generic solution to be tailored on demand

"   To "   a repository of model, algorithms,

components "   In order to deliver

"   Performances "   Scalability "   Flexibility "   Durability

Page 7: MDE based FPGA physical Design Fast prototyping with Smalltalk

LEGACY

Page 8: MDE based FPGA physical Design Fast prototyping with Smalltalk

Front end

"   High level synthesis (compilation)

"   Ressources allocation (logic synthesis)

C code

Circuit

Page 9: MDE based FPGA physical Design Fast prototyping with Smalltalk

Programming an FPGA in 4 steps

Page 10: MDE based FPGA physical Design Fast prototyping with Smalltalk

Testbenches HW Prototype

Compilation Simulation Validation

Exploration

Application Compiler Testbenches HW Prototype

Synthesizer

Synthesis/Compilation Simulation Validation

P&R Bitstream generator

Configuration Controller

10

Spécification Architecture

Architecture specification

ADL Description

ADL Based EDA generators

Page 11: MDE based FPGA physical Design Fast prototyping with Smalltalk

Zone Resources

ADL Description

Bitstream model

Resource model

Bistream Architecture VHDL

Configuration controller

Simulation & synthesis

Configuration model

Reconfigurable zones

description

Prototype

Zone Zone

Context

11

Behavioral code

Our flow

Page 12: MDE based FPGA physical Design Fast prototyping with Smalltalk

12

Some examples

Page 13: MDE based FPGA physical Design Fast prototyping with Smalltalk

RE-DESIGN

Page 14: MDE based FPGA physical Design Fast prototyping with Smalltalk

Goal oriented view extraction

Page 15: MDE based FPGA physical Design Fast prototyping with Smalltalk

Tool engine

Page 16: MDE based FPGA physical Design Fast prototyping with Smalltalk

Models as common vocabulary

Page 17: MDE based FPGA physical Design Fast prototyping with Smalltalk

Combinational circuit modeling

Page 18: MDE based FPGA physical Design Fast prototyping with Smalltalk

Target modeling

Page 19: MDE based FPGA physical Design Fast prototyping with Smalltalk

Re-design / copy down

Page 20: MDE based FPGA physical Design Fast prototyping with Smalltalk

CONCLUSION

Page 21: MDE based FPGA physical Design Fast prototyping with Smalltalk

Let’s try to summarize

"   Succes: target, tool flow

Page 22: MDE based FPGA physical Design Fast prototyping with Smalltalk

Conclusion

"   Future work: "   Tools integration (eg Mondrian integration) "   Performances improvement "   Test coverage "   Algorithm pick and play GUI

Thank you for your attention