S emb t7-arch_bus

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Maths is not everything

Embedded Systems4 - Hardware Architecture

CPUInput/Output mechanisms

Memory Buses and Aux I/O

Input/Output interfacesPower Management

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CPU Buses

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CPU bus

Connects CPU to:memory;

devices.

Protocol controls communication between entities.

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Bus protocol

Determines who gets to use the bus at any particular time.Governs length, style of communication.

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Four-cycle handshake

Basis of many bus protocols.Uses two wires:

enq (enquiry);

ack (acknowledgment).

dev1 dev2

enq

ack

data

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Four-cycle example

time

enq

ack

data

1

2

3

4

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Typical bus signals

Clock.R/W’: true when bus is reading.Address: a-bit bundle.Data: n-bit bundle.Data ready’.

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Timing diagrams

time

A

B

C

zero

one

rising falling

stable

changing

10 ns

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Typical bus timing for read

CPU:set R/W’=1;

asserts address, address enable.

Memory:asserts data;

asserts data ready’.

CPU:deasserts address, address enable.

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Bus read state diagram

Getdata Done

Adrs

Wait

See ack

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Transaction types

Wait state:state in a bus transaction to wait for acknowledgment.

Disconnected transfer:bus is freed during wait state.

Burst:multiple transfers.

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Auxiliary MechanismsTimers

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Timers and counters

Very similar:a timer is incremented by a periodic signal;

a counter is incremented by an asynchronous, occasional signal.

Rollover causes interrupt.

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Timers

The main applications of timers are to:generate events of fixed time-period

allow periodic wakeup from sleep of the device

count transitional signal edges

replace delay loops allowing the CPU to sleep between operations, consuming less power

maintain synchronization clocks

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Timers (MSP430)

System timing is fundamental for real-time applicationsThe MSP430F2274 has 2 timers, namely Timer_A and Timer_BThe timers may be triggered by internal or external clocksTimer_A and Timer_B also include multiple independent capture/compare blocks that are used for applications such as timed events and Pulse Width Modulation (PWM)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

(Used by Timer_B) TxSSELx IDx MCx - TxCLR TxIE TxIFG

Bit Description 9-8 TxSSELx Timer_x clock source: 0 0 ⇒ TxCLK

0 1 ⇒ ACLK 1 0 ⇒ SMCLK 1 1 ⇒ INCLK

7-6 IDx Clock signal divider: 0 0 ⇒ / 1 0 1 ⇒ / 2 1 0 ⇒ / 4 1 1 ⇒ / 8

5-4 MCx Clock timer operating mode: 0 0 ⇒ Stop mode 0 1 ⇒ Up mode 1 0 ⇒ Continuous mode 1 1 ⇒ Up/down mode

2 TxCLR Timer_x clear when TxCLR = 1

1 TxIE Timer_x interrupt enable when TxIE = 1

0 TxIFG Timer_x interrupt pending when TxIFG = 1

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Timers (MSP430) - TxCTL Control Register

MCx Mode Description 0 0 Stop The timer is halted. 0 1 Up The timer repeatedly counts from 0x0000 to

the value in the TxCCR0 register. 1 0 Continuous The timer repeatedly counts from 0x0000 to

0xFFFF. 1 1 Up/down The timer repeatedly counts from 0x0000 to

the value in the TxCCR0 register and back down to zero.

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Timers (MSP430) - 4 Modes of Operation

Timer reset by writing a 0 to TxRClock timer operating modes:

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Timers (MSP430) - Timer Modes

Up Mode

C o n t i n u o u s Mode

Up/Down Mode

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Timers (MSP430): Timer_A Example

Use Timer A to interrupt every 1 msSMCLK .set 1200000 ; 1200000 clocks / secondTIME_1MS .set 1000 ; 1 ms = 1/1000 s

TA_CTL .set TASSEL_2+ID_0+MC_1+TAIE ; SMCLK, /1, UP, IETA_FREQ .set SMCLK/TIME_1MS ; clocks / 1 ms

clr.w &TAR ; reset timerA mov.w #TA_CTL,&TACTL ; set timerA control reg mov.w #TA_FREQ,&TACCR0 ; set interval (frequency) bis.w #LPM0+GIE,SR ; enter LPM0 w/interrupts jmp $ ; will never get here!

TA_isr: ; timer A ISR bic.w #TAIFG,&TACTL ; acknowledge interrupt; <<add interrupt code here>> reti

.sect ".int08" ; timer A section .word TA_isr ; timer A isr

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Watchdog timer

Watchdog timer is periodically reset by system timer.If watchdog is not reset, it generates an interrupt to reset the host.

host CPU watchdogtimer

interrupt

reset

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Watchdog Timer (MSP430)

The primary function of the watchdog timer+ (WDT+) module is to perform a controlled system restart after a software problem occurs.

If the selected time interval expires, a system reset is generated.

If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

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Watchdog Timer (MSP430)

Features of the watchdog timer+ module include:

Four software-selectable time intervals

Watchdog mode

Interval mode

Access to WDT+ control register is password protected

Control of RST/NMI pin function

Selectable clock source

Can be stopped to conserve power

Clock fail-safe feature

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Watchdog Timer (MSP430) - Watchdog Power-up

After a power-up clear (PUC), the WDT+ module is automatically configured in the watchdog mode with an initial 32768 clock cycle reset interval using the DCOCLK.

The user must setup or halt the WDT+ prior to the expiration of the initial reset interval.

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RESET: ! mov.w #0x0300,SP ; Initialize stack pointer ! mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT ! bis.b #0x0f,&P1DIR ; Set P1.0-3 output ! mov.w #0,r14

...

Watchdog (MSP430) example: stoping it

In Assembly

In C

passwd = 0x5A

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Auxiliary I/OButtons & Displays

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Switch debouncing

A switch must be debounced to multiple contacts caused by eliminate mechanical bouncing:

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Encoded keyboard

An array of switches is read by an encoder.N-key rollover remembers multiple key depressions.

row

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LED

Must use resistor to limit current:

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Auxiliary I/ODAC & ADC

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Digital-to-analog conversion

Use resistor tree:R

2R

4R

8R

bn

bn-1bn-2bn-3

Vout

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Flash A/D conversion

N-bit result requires 2n comparators:

encoder

Vin

...

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Dual-slope conversion

Use counter to time required to charge/discharge capacitor.Charging, then discharging eliminates non-linearities.

Vin timer

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Sample-and-hold

Required in any A/D:

converterVin

Technology

S emb t7-arch_bus