Session one

http://www.bized.co.uk

Copyright 2006 – Biz/ed

Prepared by Alaa Salah Shehata Mahmoud A. M. Abd El Latif Mohamed Mohamed Tala’t Mohamed Salah Mahmoud

Version 02 – October 2011

Session 1



-Introduction to VHDL

- ASIC & FPGA Design flow

-How to read and write VHDL code

- Library and package

- Entity

- Basic data types

- Architecture

- Demo no. 1

Using Xilinx and Modelsim tools

1 Contents

2



Session 1

3

Introduction to VHDL



Boolean equations are impractical for large design containing hundreds of flip flops

because it could result in a huge number of logical equations.

Session 1

Designing with Boolean Equations

X= A.B

4



-Schematic based design expanded the

capabilities of Boolean equations.

-The major drawback of traditional design

methods is the manual translation of design

description into a set of logical equations.

-This step can be entirely eliminated with

hardware description languages (HDLs).

Session 1

Schematic based design

5



Question:

How do we know that we have not made a mistake when

we manually draw a schematic and connect components

to implement a function?

Answer:

By describing the design in a high-level [such as (c,

basic…)] language, we can simulate our design before

we manufacture it. This allows us to catch design errors,

i.e., that the design does not work as we thought it would.

• Simulation guarantees that the design behaves as it

should.

HDL is short for Hardware Description Language

Session 1

Hardware Description Language [HDL]

6



-Very high speed integrated circuit Hardware Description Language

-Early 1980s : It was developed by the U.S. Department of Defense

-1987 : IEEE Std 1076 - 87

-1993 : Added some new features and became IEEE Std 1076 – 93

-1999 : An extension to the language called VHDL – AMS

Analog Mixed Signal extension

-2008: IEEE Std 1076 – 2008 (New features)

Session 1

What is VHDL ?

7



Session 1

Design Flow

8



Session 1

ASIC and FPGA Design Flow Specifications

System Level

Design

RTL Description Function

Verification

Synthesis Gate Level

Simulation

Place

&Route

Configuration

FPGA Fabrication

ASIC

9



Specification is an set of requirements before designing the system

RTL Description Register-Transfer Level (RTL)

Function Verification Does this proposed design do what is intended?

Synthesis Convert RTL description into a H/W.

Placement Deciding where to place all electronic components.

Routing Wiring the placed components

This last two steps depend on the rules and limitations of the manufacturing process.

Session 1

ASIC and FPGA Design Flow

10



There is two types of tools

that deal with VHDL

-Simulation

to test the logic design using simulation

models ―All Language syntax used‘‘

-Synthesis

to convert codes to hardware

―pare of Language syntax used‖

Session 1

VHDL Language Scope

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Session 1

How to read VHDL code

12



Session 1

Library and Package

The first lines that you will find at the top of any project

Library and Packages define special types used in the code;

13



There are two types of design units in VHDL

–Primary

Not dependent upon other design units

Entity (Interface)

How the system will communicate with the outside world

–Secondary

Depends on primary design unit

Architecture (Function )

–What the system should do ?

-No secondary can exist as stand-alone—without the primary

-Whenever the primary design unit changes, the secondary design must be

reanalyzed

Session 1

Design Units

?

14



Session 1

Entity

Define ports (inputs and outputs) of the module

i.e the interface of the block

Entity declaration

entity <entity_name> is

port (

<port_name> : <mode> <type>;

<port_name> : <mode> <type>;

…

<port_name> : <mode> <type>

);

End <entity_name> ;

15



Session 1

- <entity_name> Define the port name

- VHDL is case Insensitive ----- Important Note

- Don‘t start the port name or entity name of the port with Underscore _ or number

- <mode> Define the port direction

IN : Only read from it

OUT : Only write on it

INOUT : read from or write on it (controlled by another signal)

- <type> Define the port data type

--------------------------------------------------------------------------------------------

- Last port has no semicolon ;

- Line Comments started by - -

- Comma , can separate ports with the same type and mode

- A,b : in bit ;

16

Entity



Question

17

System A is composed of system B,C and D.

Determine the entity of system A?

Session 1



• Entity of 2-input AND Gate

Session 1

Example 1

AND Gate

A C

B

18



ENTITY AND_GATE IS

port ( a : in BIT;

b : in BIT;

C : out BIT

); -- inputs and outputs of the entity

END ENTITY AND_GATE ;

Important Note

to make a comment in VHDL you can put (--) before any line you need it to be a

comment.

Session 1

Entity of 2-input AND Gate

AND_GATE

A

C B

19



BIT

BIT_VECTOR :

1D-array each element of the BIT type

Example:

a : in BIT;

b : in BIT_VECTOR (3 downto 0);

c : in BIT_VECTOR (0 to 3);

Session 1

Basic data types

STD_LOGIC

STD_LOGIC_VECTOR :

1D-array each element of the STD_LOGIC type

Example:

a : in STD_LOGIC;

b : in STD_LOGIC_VECTOR(3 downto 0);

c : in STD_LOGIC_VECTOR(0 to 3);

0 1 0 1

X W

H L

Z -

U

Default

value

Default

value

20

VHDL is strongly typed



Session 1

Basic data types

To define std_logic data type

LIBRARY ieee;

USE ieee.std_logic_1164 .all;

0 1 X

W H L

Z

-

U

Unknown

Weak Unknown

High Impedance

Don‘t care

Strong Zero

Strong One

Weak One

Weak Zero

Unitialized Default value

21



• Entity of 2-input AND Gate

using STD_LOGIC type

Session 1

Example 2

AND Gate

A C

B

22



LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY AND_GATE IS

port ( a : in STD_LOGIC;

b : in STD_LOGIC;

C : out STD_LOGIC

);


Session 1

Entity of 2-input AND Gate using STD_LOGIC type

AND_GATE

A C

B

23



Session 1

Architecture

Describe the operation (relations between inputs and outputs) of the module

i.e the Body of the block

Architecture declaration

architecture <arch_name> of <entity_name> is

-- architecture declarations

begin

-- architecture body

end <arch_name> ;

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Session 1

Architecture

Non-Blocking assignment <=

c <= a and b ;

Note

-the LHS Outputs only as we write on it

-the RHS Inputs only as we read from it

and make operations on it

To assign a value in std_logic or bit type

c <= „0‟; or c <= „1‟;

To assign a value in std_logic_vector or bit_vector type

c <= “10……1001”;

25



• 2-input AND Gate

Session 1

Example 3

AND Gate

A C

B

26



LIBRARY ieee;


ENTITY AND_GATE IS

port ( a : in std_logic;

b : in std_logic;

C : out std_logic

); -- inputs and outputs of the entity


ARCHITECTURE behave OF AND_GATE IS

BEGIN

c <= a and b; --non blocking assignment

END ARCHITECTURE behave;

Session 1

2-input AND Gate

AND_GATE

A C

B

27



• N-bits AND Gate

Session 1

Example 4

AND Gate

A C

B

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LIBRARY ieee;


USE ieee.std_logic_arith.all;

ENTITY and_gate IS

port ( A : in std_logic_vector (3 downto 0);

B : in std_logic_vector (3 downto 0);

C : out std_logic_vector (3 downto 0)

);

END ENTITY and_gate ;

ARCHITECTURE behave OF and_gate IS

BEGIN

c<= a and b;

END ARCHITECTURE behave;

Important Note

If we need to use a specific bit in vector C,A or B

If we want to put ‗1‘ onsode 2nd bit in vector C then we say C(1)

ex : c(2) <= ‗1‘;

Session 1

29

Functional/behavioral

Implementation

Interface definition

(input/output ports)

Libraries & Packages headers



Session 1

30

Using Xilinx and Modelsim tools



Writing code that describe the Entity and Architecture of 2-XOR Gate of 2 bit width,

Simulating it on Modelsim and using Xilinx ISE synthesis tool.

Session 1

A

B

C

2

2

2

31

XOR



Assignment

Session-1

Read Session-1 Notes carefully to be ready

for the next session‘s QUIZ

32

Session 1



Download Session 1 material

Introduction to the course.pdf Session 1.pdf Demo 1.txt

Ask for the material through mail

[email protected]

Facebook group

[email protected]

Session 1

33



Questions

Session-1

Session 1

34



Take Your Notes Print the slides and take your notes here

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Session 1

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See You Next Session

Session 1

36

Technology

Session one