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Gigabit LVDS Signalling on a PCB assisted by Simulation andS-Parameter Modelling John Berrie

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Topics

• Low Voltage Differential Signalling (LVDS)– Why LVDS is so popular– How LVDS works– Pushing the envelope

• Essential PCB Routing Considerations– Designing for low-cost manufacture

‒ Limitations of hardware compensation‒ Benefits of routing tuning

– Propagation modes

• Basics of S-Parameters– Time domain/frequency domain conflicts in simulation– Transforming frequency-domain models for time-domain simulation

• Simulation– When simulation is essential– Putting it together

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Why LVDS is so Popular

• Common-mode noise rejection• Low voltage• Low power• Low noise emissions and susceptibility• Compatible with gigabit speeds• High availability of standard parts

– PCI Express– FPGA– HyperTransport

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Current-Mode Drivers

3.5mA

100Ω

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Simplex

RDIFF

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Dual Simplex

PCI Express Lane

Rt

Rt

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PCI Express Features

• Introduced by Intel in 2004• High-speed serial bus replacement for PCI, PCI-X, AGP

– Software-compatible with PCI

• Point-to-point differential, dual simplex• One dual simplex (two differential pairs) equal one lane• Capacity per lane

– Version 1.x, 1.25GHz, 250MB/s– Version 2.0, 2.5GHz, 500MB/s– Version 3.0, 4GHz, 1GB/s– Largest common lane count is 16 per bus

• Data transmitted in packets– 8B/10B encoding balances ones and zeros– Clock embedded within data

‒ Major implications for PCB routing

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Skew Matching in PCI Express

• Most critical– Within each differential pair

‒ Align within a unit interval (one clock period)

• And then ...– Within each 2-differential-pair dual simplex lane

‒ Desirable to make bidirectional operating speed more consistent

• And then ...– From lane to lane

‒ Depends on minimum packet size‒ Align within (bits in packet) unit intervals

‒ e.g. 128-bit packet means align within 128 unit intervals

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HyperTransport Features

• Dual simplex point-to-point• 200MHz to 3.2GHz• 32-bit full-speed up to 51.2GB/s• Packet-based• Separate clock and data• Point-to-point dual simplex routing with Tunnel devices to create

daisy chains, stars and other topologies

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Important PCB Routing Considerations for HyperTransport

• Data and commands are combined and transmitted in packets• Clock and control are separate from data

– Clock to data skew constraints are required

• 2, 4, 8, 16 or 32 bit data path• Designed to work on low-cost FR-4, including 4-layer boards• On-die bridge termination• Maximum route length up to around 0.75 metres, depending on

layer stack

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HyperTransport 3.1 Signal Groups in one Link

• All differential pairs• One CLK line per <=8

CAD lines • One CTL line per <=8

CAD lines (Gen3)• Skew constraints

between CAD, CTL and CLK

Low-speed signals PWROK and RESET# omitted from this diagram

CAD=Command/Addr/Data[p:0]

CAD=Command/Addr/Data[p:0]

CTL=Control[n:0]

CTL=Control[n:0]

CLK=Clock [m:0]

CLK= Clock [m:0]

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Hardware Compensation

• Pre-emphasis– Boost relative high frequency content (considering frequency domain)

‒ Higher-frequency content related to rise time and amplitude– Stronger state change (considering time domain)– Compensates for Inter-Symbol Interference (ISI) during rapid state changes

• Timing– Simplifying required route topology

• Impedance– Adapt to detected PCB electrical characteristics (characteristic impedance)

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Differential Pair Essentials

• Symmetry is key

Connector Pads (driven end)

Series AC Coupling Capacitors

Signal Vias and Ground Stitching Vias Component

Pads (receiving end)

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+

GND

GAPGND

Differential Pair Essentials

• Avoid significant en-route discontinuities and imbalance– Simulate to check consequences of small discontinuitiesINSULATOR

- + -

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Uniformity = Predictability

• Design to avoid subtle glitch culprits– Environmental factors– Undetected manufacturing

tolerance violations

• Design from the front end– Tune to exceed

performance‒ Improves re-usability

aa

a

bb

• Keep coupling uniform– Predictable performance from the start– Avoids simulator stress– Electrically-equivalent PCB layers– Uniform differential spacing– Uniform pair-to-pair spacing and parallelism

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Desirable Field Lines in Differential Pairs

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Propagation Modes

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S-Parameters

• Useful for modelling high-speed passive components such as filters and connectors

• Black box modelling technique– Can be derived from hardware with no need to understand internal

behaviour

• Unlimited in frequency• Each entry relates to a single frequency

– Large set of entries needed to cover component frequencies of a digital signal

• Each entry describes how a wave of a single frequency arriving at a single port is transformed in terms of relative amplitude and phase as it is scattered to the other ports

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S-Parameters

• Scattering of wave arriving at Port 1 (reverse for arrival at Port 2)

Port 1 Port 2

Zo

Zo

a1 b1 b2

=S11a1 =S21a1

• Scattering matrix for wave arriving at Port 1 or Port 2

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S-Parameter Model of Transmission Line

V2V1V0 50Ω

50Ω

100Ω 585.0585.0135828.00707.0

135293.02

V

V2

0

2

1

21221 j

a

bSS

000.0321.00321.001707.0

467.021

V

V2

O

1

1

12211 j

a

bSS

200mm

V0=1V peak=0.707V RMS

V2=0.414V peak=0.293V RMS,135° phase shift with respect to V0

V1=0.66V peak=0.467V RMS

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!2-Port S-parameters for 100Ω lossless transmission line with two frequency points in Magnitude/Angle format

# MHz S MA R 50

200.000 0.321 0.000 0.828 238.000 0.828 135.000 0.321 0.000

250.000 0.321 0.000 0.828 135.000 0.828 135.000 0.321 0.000

Touchstone® File Format for S-Parameters

Frequency Units Parameters Type

Magnitude/Angle Normalize to 50Ω Source/Load

S11 S21 S12 S22Frequency

Alternative formats are DB (dB-angle) and RI (real-imaginary)

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Passive Component Modelling

• S-Parameter Model– Black box model so no

assumptions– Valid only under tested

conditions– Need to cover entire expected

frequency range– Frequency domain

• Passive Network Model– Extrapolates and interpolates

automatically– May lose validity at higher

frequency– Only models what is included– Frequency or time domain

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Differential Channel with Common-Mode Filter: S-Parameter or Obfuscated Passive Network Model

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Simulation with Model Choices:S-Parameter or Obfuscated Passive Network Model

IBIS buffer model + S-Parameter driver model simulation

HSPICE transistor-level Model + obfuscated passive model simulation

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Combined-Function Passive Devices

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Conclusion

• Point-to-point differential signalling is common and increasingly standardised

• Ultra-fast data with low power being used whether needed or not– Compare DDR2/DDR3 memory

• Cheapness of manufacture has been considered– Adaptive signalling techniques– Simplified topology– Tolerance of PCB electrical characteristic variations

• But…– For high-volume/cost-reduced, non-standard or safety-critical designs,

simulation is still essential‒ And it's still advisable in all cases, even when following design rules

The Partner for Success

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