kunal-ghosh-vlsisystemdesigncom documents

Common clock path pessimism removal
Technology Common clock path pessimism removal
The Big Question
Engineering The Big Question
Clk-to-q delay, library setup and hold time
Technology Clk-to-q delay, library setup and hold time
Regular buffer v/s Clock buffer
Technology Regular buffer v/s Clock buffer
Circuit design & SPICE simulations
Engineering Circuit design & SPICE simulations
On-Chip Variation
Technology On-Chip Variation
SPEF format
Technology SPEF format
Signal Integrity (SI glitch)
Technology Signal Integrity (SI glitch)