1-GSample/s 6-Bit Time-Interleaved SA-ADC Illinois Center...

1-GSample/s 6-Bit Time-Interleaved SA-ADC Arrays with Background Digital Calibration

Wenbo Liu, Paritosh Bhoraskar, Yuchun Chang and Yun Chiu

Illinois Center forWireless Systems

Motivation & Approaches Time Interleaved ADC Arrays• To implement a high-speed

ADC with relatively slow circuits.

• Static channel mismatches– Offset, gain, linearity

mismatch• Dynamic channel

mismatches– Timing skew, jitter

The Proposed Architecture• Single track/hold amplifier (THA)

– Immune to timing skew and jitter

• Time-interleaved ADC array– 10 100MSample/s SA-ADC– Adaptive digital filter (ADF)– Correct static channel

mismatches• Reference conversion path

– Slow but accurate – Provide ADFs with accurate

digital codes • A DLL generating all timing

signal with desired phases

Linear Equalization

• Linear equalizer– ADF taps track each bit’s weight and the offset– Taps are updated with the sampling rate of the reference ADC– All calibration is performed in the digital domain

Major Circuit Analog Nonidealities

• Analog impairments:– Mismatch of small capacitors degrading linearity– Stray capacitor (Cp) causing sampling gain loss– Comparator offset & charge injection (Q)

resulting in an input referred offset, Vos,input .

• Static error model

p

n

iitotqninputosRi

n

i tot

iin CCCCwhereVVVd

CCV ++=++−= ∑∑

−

=

−

=0

1

0,

1

0

,)12(

Sine-wave Test

Performance600 mW5.0 / 6.01.3GS/s2003

310 mW4.7 / 6.02GS/s2005

This work2006

2004

Year

30 mW>5.5bit1GS/s55 mW5.3 / 6.01GS/s

774 mW7.26 / 8.01.6GS/s

PowerENOB (bit)Fs

Note: The performance of this work is estimated based on post-layout simulation.

Channel SAR ADC SHAReference ADCReference ADC clock generatorDLL

Bias network

Extension to Flash ADC

• Modern high-speed communication systems create urgent demands on ADC

– Next generation UWB wireless technology– High bit rate optical communication system

• The sampling rate versus power consumption– Super linear trade off for high-speed ADC– Solution: Time interleaved architecture

• Fabrication technology advancement– Digital circuits: Unprecedented speed, higher integration level– Analog circuits: SCE, low supply voltage, process variation– Solution: Adaptive digital calibration corrects analog impairment

• Single channel ADC is simulated with all analog nonidealities• Use pure sine wave as input• Conversion errors are calibrated

• Apply the similar idea to a 10GS/s 6-bit flash ADC

• Minimal sized comparators– Reduce input capacitance– Reduce power

• Large comparator offset– Cancelled by the

trimmable voltage sources• ADF

– Compare reference ADC and flash ADC output

– Generate control codes

0 1 2 3 4 5

x 107

-80

-60

-40

-20

0PSD before Calibration

Hz

dB(N

orm

aliz

ed) SFDR=22.6dB

ENOB=3.03bit

0 1 2 3 4 5

x 107

-80

-70

-60

-50

-40

-30

-20

-10

0PSD after Calibration

Hz

dB(N

orm

aliz

ed) SFDR=50.9dB

ENOB=5.92bit

Ref.A/DM

ADF

Vin

Trimmable votage source

Full flash ADC