A 6.1mW Dual-Loop DLL with 4.6ps RMS JitterParitosh Bhoraskar and Yun Chiu

Illinois Center forWireless Systems

DLL Applications• Delay-variation

compensation in Fiber-Optic Comm.

• Integral part of Clock-Data Recovery (CDR) Blocks in Wireline and Wireless Communication Solutions

• Target Application: Interleaved ADC array require multiple phases of a clock aligned with another clock at different frequency

Window Based Phase Detector

• Replica delay line and DAC used to generate timing window that tracks input reference

• Three state PD with UP/DN and HOLD state. Digital control word frozen in HOLD state

• Relaxed PD design spec due to timing window• Power saving in Digital Control in HOLD state

Q

QSET

CLR

D

Q

QSET

CLR

D

Ref

In

Window

Dn

Up

Ref

Out

Window UP: Low, DN: High(Shift Right)

UP: High, DN: High(Lock)

UP: High, DN: Low(Shift Left)

Major Tradeoffs

• Control-word limit cycle dominates Jitter

• Fine LSB and high power required for low jitter

• Window-ed PD eliminates limit cycle based jitter

• Low Jitter and low power solution

• Cost: Larger static phase error

LSB sizeA

rea/

Pow

er C

onsu

mpt

ion

Jitter

PowerJitterJitter (window PD)

Digital Control Logic

• Startup Successive Approximation Binary search

• Harmonic Lock avoided by starting with min delay using reset. Duty-cycle free harmonic lock detection also implemented to eliminate false lock

• Underflow/Overflow based stuck locks corrected by confining delay-line delay s.t. T/2 < Delay <3T/2

• Implemented by inverting Phase Detector decision based on ‘Monitor’ signal

0.5 Tref 1.5 Tref

Ref

Stuck Lock

False Lock

Stuck LockResolved

Ref

Out

PD_UP

PD_DN

Sys_clk

Underflow

Monitor

Inc

Dec

Stuck Lock

Measurement Results

DAC2

DAC1DACrep

DL1DLrep

LF

DL

2

PD

Output Driver

0.83mm

0.84m

m

6.15.65.14.8Power (mW)

4.64.76.19.1RMS Jitter (ps)

1.20.80.40.2f2(GHz)

120804020f1(MHz)

Results at Vdd = 1.25V, T = 25°C across 5 working chips

• DLL fabricated in 0.13um process• Active die area

400 X 600 m2

• Total Die Area 830x840 m2

• Low RMS jitter attained for low power

Proposed Architecture

• One loop completely inside another approach as opposed to usual cascaded loop dual-loop architecture

• Inner Loop generates 10 uniform output phases for interleaved ADC channels

• Outer Loop aligns all these phases to faster reference clock used by Sample and Hold of the ADC fouter

PD1 LF1 DAC1

PD2LF2DAC2

CLK

Phase1 Phase 10Phase 2

Replica Delay Cell

Main Delay CellCLK

Inner Loop

Delay Cell

DACrepOffset

finner