View
225
Download
0
Category
Preview:
Citation preview
8/12/2019 1. MOS Tran Theory
1/42
VLSI Design
MOS Transistor Theory
8/12/2019 1. MOS Tran Theory
2/42
Silicon Semiconductors
Modern electronic chips are built mostly on silicon substrates
Silicon is a Group IV semiconducting material
crystal lattice: covalent bonds hold each atom to four neighbors
Si SiSi
Si SiSi
Si SiSi
8/12/2019 1. MOS Tran Theory
3/42
Modern transistors are few microns wide and approximately
0.1 micron or less in length
Human hair is 80-90 microns in diameter
8/12/2019 1. MOS Tran Theory
4/42
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents
between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between
source and drain
Low power allows very high integration
First patent in the 20s in USA and Germany
Not widely used until the 60s or 70s
8/12/2019 1. MOS Tran Theory
5/42
MOS Transistors
Four terminal device: gate, source, drain, body
Gateoxidebody stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2(oxide) is a good insulator (separates the gate from the body
Called metaloxidesemiconductor (MOS) capacitor, even though gate ismostly made of poly-crystalline silicon (polysilicon)
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
NMOS PMOS
8/12/2019 1. MOS Tran Theory
6/42
Transistor structure
n-type transistor:
8/12/2019 1. MOS Tran Theory
7/42
NMOS Operation
Body is commonly tied to ground (0 V)
Drain is at a higher voltage than Source
When the gate is at a low voltage: P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+D
0
S
8/12/2019 1. MOS Tran Theory
8/42
NMOS Operation Cont.
When the gate is at a high voltage: Positive charge on gateof MOS capacitor Negative charge is attracted to body under the gate
Inverts a channel under gate to n-type (N-channel, hence
called the NMOS) if the gate voltage is above a threshold voltage(VT)
Now current can flow through n-type silicon from sourcethrough channel to drain, transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
8/12/2019 1. MOS Tran Theory
9/42
PMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Drain is at a lower voltage than the Source
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
8/12/2019 1. MOS Tran Theory
10/42
CMOS Fabrication
CMOS transistors are fabricated on siliconwafer
Wafers diameters (200-300 mm)
Lithography process similar to printing press On each step, different materials are
deposited, or patterned or etched
Easiest to understand by viewing both top andcross-section of wafer in a simplifiedmanufacturing process
8/12/2019 1. MOS Tran Theory
11/42
8/12/2019 1. MOS Tran Theory
12/42
Well and Substrate Taps
Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor
connection called Schottky Diode
Use heavily doped well and substrate contacts/taps (orties)
n+
p substrate
p+
n well
A
YGND VDD
n+p+
substrate tap well tap
n+ p+
8/12/2019 1. MOS Tran Theory
13/42
Inverter Mask Set
Top view Transistors and wires are defined by masks
Cross-section taken along dashed line
GND VDD
Y
A
substrate tap well tap
nMOS transistor pMOS transistor
8/12/2019 1. MOS Tran Theory
14/42
Detailed Mask Views
Six masks
n-well
Polysilicon
n+ diffusion
p+ diffusion
Contact
Metal
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
InIn reality >40 masks
may be needed
8/12/2019 1. MOS Tran Theory
15/42
Fabrication Steps
Start with blank wafer (typically p-type where NMOS is created) Build inverter from the bottom up
First step will be to form the n-well (where PMOS would reside)
Cover wafer with protective layer of SiO2(oxide)
Remove oxide layer where n-well should be built
Implant or diffuse n dopants into exposed wafer to form n-well
Strip off SiO2
p substrate
8/12/2019 1. MOS Tran Theory
16/42
Oxidation
Grow SiO2on top of Si wafer
9001200 C with H2O or O2in oxidationfurnace
p substrate
SiO2
8/12/2019 1. MOS Tran Theory
17/42
Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic polymer
Property changes where exposed to light
Two types of photoresists (positive or negative) Positive resists can be removed if exposed to UV light
Negative resists cannot be removed if exposed to UV light
_
p substrate
SiO2
Photoresist
8/12/2019 1. MOS Tran Theory
18/42
Lithography
Expose photoresist to Ultra-violate (UV)light through the n-well mask
Strip off exposed photoresist with
chemicals
p substrate
SiO2
Photoresist
8/12/2019 1. MOS Tran Theory
19/42
Etch Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
N-well pattern is transferred from the mask to
silicon-di-oxide surface; creates an opening to thesilicon surface
p substrate
SiO2
Photoresist
8/12/2019 1. MOS Tran Theory
20/42
Strip Photoresist
Strip off remaining photoresist Use mixture of acids called piranah etch
Necessary so resist doesnt melt in next step
p substrate
SiO2
8/12/2019 1. MOS Tran Theory
21/42
n-well n-well is formed with diffusion or ion implantation
Diffusion
Place wafer in furnace with arsenic-rich gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si
SiO2 shields (or masks) areas which remain p-type
n well
SiO2
8/12/2019 1. MOS Tran Theory
22/42
Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
p substrate
n well
8/12/2019 1. MOS Tran Theory
23/42
Polysilicon(self-aligned gate technology)
Deposit very thin layer of gate oxide < 20 (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon
Heavily doped to be good conductor
Thin gate oxide
Polysilicon
p substraten well
8/12/2019 1. MOS Tran Theory
24/42
Polysilicon Patterning
Use same lithography process discussed earlier topattern polysilicon
Polysilicon
p substrate
Thin gate oxide
Polysilicon
n well
8/12/2019 1. MOS Tran Theory
25/42
8/12/2019 1. MOS Tran Theory
26/42
N-diffusion/implantation
Pattern oxide and form n+ regions
Self-aligned processwhere gate blocks n-dopants
Polysilicon is better than metal for self-aligned gatesbecause it doesnt melt during later processing
p substraten well
n+ Diffusion
8/12/2019 1. MOS Tran Theory
27/42
N-diffusion/implantation cont.
Historically dopants were diffused
Usually high energy ion-implantation usedtoday
But n+ regions are still called diffusion
n wellp substrate
n+n+ n+
8/12/2019 1. MOS Tran Theory
28/42
N-diffusion cont.
Strip off oxide to complete patterning step
n wellp substrate
n+n+ n+
8/12/2019 1. MOS Tran Theory
29/42
P-Diffusion/implantation
Similar set of steps form p+ diffusionregions for PMOS source and drain andsubstrate contact
p+ Diffusion
p substraten well
n+n+ n+p+p+p+
8/12/2019 1. MOS Tran Theory
30/42
Contacts
Now we need to wire together the devices
Cover chip with thick field oxide (FO)
Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+n+ n+p+p+p+
Contact
8/12/2019 1. MOS Tran Theory
31/42
Metalization
Sputter on aluminum over whole wafer Copper is used in newer technology
Pattern to remove excess metal, leaving wires
p substrate
Metal
Thick field oxide
n well
n+n+ n+p+p+p+
Metal
8/12/2019 1. MOS Tran Theory
32/42
Derivation of transistor characteristics
8/12/2019 1. MOS Tran Theory
33/42
MOSFET gate as capacitor
Basic structure of gate is parallel-plate capacitor:
gate
substrate
SiO2
xoxVg
+
-
+ + + + + + + + + + + +
- - - - - - - - - - - -
inversion
8/12/2019 1. MOS Tran Theory
34/42
MOS as a parallel plate capacitance
Formula for parallel plate capacitance/unit area:Cox= ox/ tox,
where toxis the thickness of the SO2in cm, and
oxis its permittivity:
ox= 3.46 x 10-13 F/cm
Gate to substrate capacitance helps determine thecharacteristics of a channel which forms an inversion region(region devoid of dopant carriers in the substrate) between
the source and drain of a MOS transistor. In particular, it playsa critical role in the determination of the threshold voltage ofa MOS transistor.
8/12/2019 1. MOS Tran Theory
35/42
Threshold voltage
The threshold voltage, Vt0, when the source to substrate voltage is 0.
Vt0= Vfb+ s+ Qb/Cox+ VIIComponents of Vt0are:
Vfb= flatband voltage between gate and substrate, i.e., the work functiondifference between gate and substrate. The work function is the energy requiredto remove an electron from the Fermi energy to the vacuum level.
sis the surface potential which is equal to twice the Fermi potentialwhere niis the intrinsic carrier (electron or hole) concentration of the substrate,kT/q is the thermal voltage, and Nais the hole concentration in the substrate.
Qb/Coxis the voltage across the capacitor, where , qis the chargeof an electron, siis the permittivity of silicon,
VII is the voltage adjustment = qDI/Cox, where DIis the ion implantationconcentration (body effect)
Qb 2qsiNas
2kT
qlnNa
ni
8/12/2019 1. MOS Tran Theory
36/42
Threshold voltage
The flat-band voltage between gate and substrate depends on the difference inthe work function between gate and substrate (gs) and on fixed surface charge(Qf):
assuming that the gate is doped with n-type carriers with the concentration of Ndp
When the source to substrate voltage is not 0 then the threshold voltage isshifted by a differential voltage, called the body effect:
Vfb gsQf
Cox
gs kT
qlnNaNdp
ni2
Vt n( sVsb s )
n 2qsiNa
Cox
8/12/2019 1. MOS Tran Theory
37/42
Body effect
Reorganize threshold voltage equation:Vt= Vt0+ Vt
Threshold voltage is a function of
source/substrate voltage Vsb. Body effect is the coefficient for the Vsb
dependence factor.
8/12/2019 1. MOS Tran Theory
38/42
Channel length modulation lengthparameter
adescribes small dependence of drain current on Vdsin saturation.
Factor is measured empirically.
New drain current equation: Id= 0.5k (W/L)(Vgs- Vt)
2(l- aVds)
Equation has a discontinuity between linear andsaturation regions---small enough to be ignored.
Note: I use ainstead of l to avoid confusion withchannel parameter l.
8/12/2019 1. MOS Tran Theory
39/42
Gate voltage and the channel
gate
drainsourcecurrent
Id
Vds< Vgs- Vt
Vgs > Vds + Vtgate
drainsourcecurrent
Id
gate
drainsource
Id
Vds= Vgs- Vt
Vgs = Vds + Vt
Vds> Vgs- Vt
Vgs < Vds + Vt
Linear region
Saturation regionInversion layer
current
Pinch offdI
d/dV
dsdecreases
Channel transconductance decreases
Inversion layer shrinks
8/12/2019 1. MOS Tran Theory
40/42
Leakage and subthreshold current
A variety of leakage currents draw currentaway from the main logic path.
The sub-threshold current is one particularly
important type of leakage current.
(When the gate voltage is just below thethreshold voltage, the point of weak-
inversion)
8/12/2019 1. MOS Tran Theory
41/42
Types of leakage current.
Weak inversion current (sub-threshold current). Punch-through currents. (When the drain to source voltage gets
to be too high, the source and drain regions may be shorted.)
Gate oxide tunneling-- Hot carriers(For short channels, electrons may accumulate into the gate oxide, leading to
changes in threshold conditions.)
Reverse-biased pn junctions Drain-induced barrier lowering (Shift in threshold level to
increase in drain voltage-- higher current flow near cut-off when the drain
voltage increases) Gate-induced drain leakage (As gate oxide layer becomes very
thin, channel current may leak into the gate-- non-ideal capacitor)
8/12/2019 1. MOS Tran Theory
42/42
Subthreshold current
Subthreshold current:
IDSW
L I eq(VGSV
T)nkT 1 eqVDSkT
2'
22
2t
SBF
AS
V
NqI
SBF Vn
221
IDSW
LI eq(VGSVT)nkT when Vds >> q/kT
log10IDS log10W
LI
q
kT
VGSVTn
log10 e
1
S1
n
q
kTln(10)Sis called the sub-threshhold swing;
smaller values of S are desirable
Recommended