Active Pixels for a new Inner Vertex Detector for STAR

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Active Pixels for a new Inner Vertex Detector for STAR

H. Wieman, F. Bieser, S. Kleinfelder, H. Matis, P. Nevski, N. Smirnoff, G. Rai

and F. Retiere

6-June-01

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Outline

D mesons, motivation for an additional inner vertex detector at STAR

Active Pixel Sensor (APS) concept under consideration

R&D effort

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The STAR detector at RHIC

Inner micro-vertex detector for inside SVT

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Motivation for an inner tracker

Measure D mesons, charm quark production Emphasized in the long range plan for STAR

» Window to early hot parton phase– Large mass, c quarks less less likely from later mixed

phase and hadron phase– More restrictive than measure of strange quark

production– Augments measurements of multi-strange particles, -

– Calibration of J/ suppression

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Technical Challenge of D mesons

Topological separation of D vertex from primary vertex with thousands of tracks» D+K-+ + 8% c = 320 m» D0 K- + 3.65% c = 125.9 m

Require microscopic vertex resolution» minimum coulomb scattering» Minimum distance to interaction to improve pointing

resolution– Therefore need excellent two track resolution

» excellent position resolution

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CCD - VXD3 at SLACa model for our approach

Very thin, 0.4% radiation length

High resolution» pixels - 20 m cubes

» surface resolution < 4 m

» projected impact parameter resolution 11 m

Close to beam, inner layer at 2.8 cm radius

307 million pixels, < 1 cent/pixel

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VXD3 almost the solution Limitations

» Slow readout – 200 ms» Radiation hardness may be a problem in the RHIC

environment. 2 kRad per year Investigating use of thinned Active Pixel

Sensors (APS) in CMOS in place of CCDs» CMOS design freedom should allow faster readout

solution» APS will have better radiation hardness since

unlike CCDs does not need long charge transport path through silicon.

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8 cm

5.6 cm

Active Pixel Sensor (APS)

20 m square pixels

5 chips per slat

90 million pixels

40 m thick chips

760 m Be beam pipe

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Can D0 be resolved?

Preliminary analysis, K-+ channel» Multiple and single coulomb scattering (full

Molière)» Impact parameter cut > 100 m from

primary vertex» p 700 MeV/c» 760 m Be beam pipe 2.2 cm radius» 40 m inner Si layer at 2.8 cm radius

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Isolating the primary vertex

Simulated pointing resolution of the Micro-vertex detector

100 m exclusion cut

xy projection (m)

simulation

gaussian fit

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Invariant mass reconstruction of D0s k (preliminary simulation)

250,000 events 5 D0s in –1<<+1 Would need 6X106 if

1 D0

» This is 2 weeks running

M (GeV)

D0

2s

BN

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Operating in the RHIC environment

Very central collision dN/d = 700 Resulting hit density on inner vertex:

14 hits/cm2

Fraction of pixels filled in a single central event at the inner radius = 0.05%

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False rejection by pileup

design luminosity, 200 ms readout» 400 hits/cm2

» 1.4% pixels filled» false rejection 0.5%

10 X design luminosity, 200 ms readout» 4000 hits/cm2

» 13% pixels filled» false rejection 11%

SVT

real hits

pileup hits

primaryvertex rejectioncut

tracking in cone of uncertainty

pileup causing false rejection

innervertexdetector

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Inner Vertex Detector Requirements

Most Critical» Must be thin < 0.2% X0

» Must be low power < 100 mW/cm2, gas cooling to be thin» Must be minimum distance from beam, excellent two

track resolution» Must survive 1 year, 2 kRad

Desirable» Readout fast enough to keep up with other detector read

out, 10 ms now, less later No interest

» Use in a trigger is not being considered

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R&D effort focusing on APS in CMOS

Can be thinned like CCDs Better radiation hardness (TSMC 0.25 m CMOS is

good to 40 MRad) Potentially faster readout and lower power since zero

suppression can be done on the detector chip Design freedom with standard industry process LEPSI demonstrated technology with minimum

ionizing particles No CMOS APS detectors operating in an experiment MIP detection depends on a feature of the CMOS

process that could disappear

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Electronics R&D plan

Copy LEPSI style APS Using what is learned from the copy

investigate possible readout schemes for power and speed» Possible directions: full fast data read vs

on chip zero suppression

Next a look at the LEPSI MIMOSA APS design

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A Monolithic Active Pixel Sensor for Charged Particle Tracking and Imaging using Standard

VLSI CMOS TechnologyJ.D. Berst et al.

LEPSI, Strasbourg

LEPSI APS» 20 m square pixels

» 64X64 array MIMOSA 1, 0.6 m CMOS MIMOSA 2, 0.35 m CMOS

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MIMOSA CHIP by LEPSI

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Properties

Chip MIMOSA I MIMOSA II Ours

Technology AMS

0.6 m

AMS

0.35 m

TSMC

0.25 m

Epi (m) 14 5 8-10

MIP from Epi (e/h) 1100 400 640-800

Cn (fF) 11 7.1 5

Gain (V/e) 15 23 32

Leakage I (fA) 27 0.25 ?

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MIMOSA Readout and noise reduction

Read out all pixels, 12 bit ADC MIMOSA I at 2.5 MHz MIMOSA II at 10 MHz Correlated Double Sample (CDS) offline

to remove Reset thermal (kTC) and Fixed Pattern noise

Average baseline subtraction to remove leakage current pedestal

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Performance

Chip MIMOSA I MIMOSA II

Pixel Noise (e rms) 11.9 9.2

S/N measured 42 22

S/N expected 31 14

S/N improvement 1.3 1.5

Spatial resolution (m) 1.4 2.2

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APS development by Stuart Kleinfelder

Previous experience» SCA for EOS, NA49 and

STAR» ATWD for Amanda and

KamLAND, 1 GHz FADC - for just milliwatts of power

» 10,000 Frame/sec video chip (thesis project)

1st step – reproduce LEPSI results

10,000 fps, every 4th frame displayed propeller speed ~ 2000 rpm

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First chip submission

128X128 pixels0.25 m CMOS2.5 voltTSMC through MOSIS

n well collection nodes

4 styles

column selection shift register

row selection shift register

S. Kleinfelder

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SK chip design

4 pixel styles Added FET acts as

» Sample and hold (off or on) or

» Capacitance isolator (TX held constant at intermediate voltage)

Copy of MIMOSA style

capacitance isolator

Cd Cg

Cd

Cg

Vsg drops to Vthreshold and any additional charge spills to drain (Cg).Only Cg is reset

Vsg

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Status of our LEPSI copy

We have chips back from MOSIS Howard Matis has first version of DAQ

ready for testing Fred Bieser is programming the readout

board which is back ready for stuffing We will test with sources and in ALS

electron beam

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Readout options depend on chip performance

If the following noise sources are low compared to the signal then simple threshold zero suppression can be used» reset kTC noise (thermal)» reset fixed pattern noise » diode leakage current

Expected MIP signal 640 e

Expected reset kTC noise: 30 to 40 Expected reset fixed pattern ? Diode leakage current 0.25 fA to 29 fA

e

kTCd

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APS Readout with Zero Suppression if noise permits

CMOS APS ARRAY

READOUT WITH EMPTY ROW DETECTION

AND COLUMN-WISE ZERO SUPPRESSION.

SE

QU

EN

TIA

L R

OW

SE

LE

CT L

OG

IC

APS COLUMN READOUT WITH CDS

THRESHOLD DISCRIMINATION

SPARSE DATA ZERO SUPPRESSION

CONTROL AND SEQUENCING LOGIC

EXTERNAL INTERFACE

•Readout of each row followed by threshold discrimination and zero suppression in columns.

•No additional logic in pixels.

•Minimal periphery in one dimension allows close abutting.

S. Kleinfelder

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Zero suppression if only reset fixed pattern noise is a problem

When a trigger occurs a CDS is done with a reset between samples. This removes reset fixed pattern noise, but not reset kTC noise.

Reset is done one row at a time. Could have a separate readout on each column.

APS PIXELRESETACESSPOWER

BIAS

I-BIAS

SAMPLE 1

SAMPLE 2VOUT1

VOUT2

APS PIXELRESETACESSPOWER

BIAS

I-BIAS

VREF

S1

S2

S3

VCDS

C1

C2

VCDS=(C1/C2)VSIG+(1+C1/C2)(VOFF/(1+A))

VOFF, A

BASIC APS READOUT WITH CORRELATED DOUBLE

SAMPLING.

APS READOUT, CDS WITH SUBTRACTION AND OP-AMP

OFFSET CANCELLATION.

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Zero suppression if large pixel to pixel variation and large reset noise

(the heroic solution)

Full independent CDS on each pixel before doing threshold check

Do by continuous digitization and store into on chip dynamic RAM in a few ms for all pixels

On trigger digitize and subtract memory value to obtain CDS for threshold check

Dynamic RAM only 1/10 pixel area Need power analysis, but experience

suggests 100 mW/cm2 limit possible

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Alternative readout mode

Full pixel readout - continuous 20 – 40 ms per read (slower than other detector

readouts) Off chip correlated double sampling Chip design may be simpler, but enhancements

required like column parallel operations etc. Complicated DAQ and data processing Filled pixels still < 3% at 10 X design luminosity Should be able to stay in 100 mW/cm2 power budget

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Mechanical Possibilities beyond VXD3 ?

Material VXD3 APS

(m) % X0 (m) % X0

Be Beam Pipe 760 0.22 600 0.17

Silicon 180 0.16 40 0.037

Kapton 0.05 0.05

Copper 17.8 0.09

Aluminum 28 0.023

Be substrate 380 0.11 40 0.011

Total 0.63 0.3

VXD3 Ladder

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Development tasks

Simulations (H. Matis, N. Smirnoff, P. Nevski) Test new chip (S. Kleinfelder, H. Matis, F. Bieser,

F. Retiere) Explore readout options (S. Kleinfelder) Develop mechanical supports and interconnects

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Conclusion

New challenging technology with unknowns

Significant potential gains Important for STAR Long Range Plan

» Could benefit other RHIC experiments and heavy ion program at LHC

~Cost 3.25 M$ ~Time 3-4 years

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APS Readout

APS PIXELRESETACESSPOWER

BIAS

I-BIAS

SAMPLE 1

SAMPLE 2VOUT1

VOUT2

APS PIXELRESETACESSPOWER

BIAS

I-BIAS

VREF

S1

S2

S3

VCDS

C1

C2

VCDS=(C1/C2)VSIG+(1+C1/C2)(VOFF/(1+A))

VOFF, A

BASIC APS READOUT WITH CORRELATED DOUBLE

SAMPLING.

APS READOUT, CDS WITH SUBTRACTION AND OP-AMP

OFFSET CANCELLATION.

S. Kleinfelder