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17/05/04 ALICE TPC Meeting Bernardo Mota (CERN PH/ED)
Progress on the RCU PrototypingBernardo Mota
CERN PH/EDOverview
Architecture
Trigger and Clock Distribution
Instruction Sequences
Current Capabilities
Present Status
On Behalf of:
Carmen Gonzalez GutierrezRoberto CampagnoloRoland BrammTorsten AltKjetil UllalandJorgen LienAre MartinsenMatthias RichterHeinz TilsnerSebastian BablokChristian Kofler
17/05/04 ALICE TPC Meeting Bernardo Mota (CERN PH/ED)
Overall Frontend System
17/05/04 ALICE TPC Meeting Bernardo Mota (CERN PH/ED)
ArchitectureF
EC
FE
CF
EC
FE
C
ALTRO bus
I2C bus
SIU InterfaceALTRO Interface
• Instruction MEM• Pattern MEM• Active channel list• Result MEM
Slow Control
Carmen GonzalezGutierrez
talk
DataAssembler32 <- 40
StatusRegisters
CommandInterpreter
&Bus Switch
DCS
DDL
RCU bus
FPGA
17/05/04 ALICE TPC Meeting Bernardo Mota (CERN PH/ED)
ALTRO Interface: Trigger ModesL1
-L2 RCU
L2
L1IF_L1
****External
-L1&L2 filter-
Final OperationMode
tw
SW
TR
G RCU L1 L2
drift time
programmableSWTRG
WAIT
exec via DCS
Data via DDL ****
L1 o
nly RCU L2L1
IF_L1
****External
-L1 filter-
Test BeamMode
17/05/04 ALICE TPC Meeting Bernardo Mota (CERN PH/ED)
0
4’h1
19
RS_STATUS 16’hxxxx
0
4’h2
19
RS_L1CNT 16’hxxxx
0
4’h3
19
RS_L2CNT 16’hxxxx
0
4’h9
19
END 16’hxxxx
0
4’h6
19
CHRDO 16’hxxxx
0
4’h7
19
PMREAD channel add.
15 12 1116
4’hx
0
4’h8
19
PMWRITEchann. add.
15 13 1116
3’hx
12
bcast
Instruction Codebook
0
4’ha
19
WAIT Nbr. Cycles CLK
16 15
0
4’h0
19
JUMP/LOOP Add.
15 8 716
N loops
0
4’hb
19
IF_TRIGGER 16’hxxxx
17/05/04 ALICE TPC Meeting Bernardo Mota (CERN PH/ED)
Examples of Instruction Sequences
RPINC
CHRDO (Readout)
WPINC (L2)
WAIT
SWTRG (L1)
*END*
Testing Multi-Event Buffer & Readout with software
trigger
From ALTROs to DAQw/ software trigger
Accessing in infinite loop a given
ALTRO Register
READ ‘N’ REG
WRITE ‘N’ REG
JUMP
Scope probing for electricalintegrity check
17/05/04 ALICE TPC Meeting Bernardo Mota (CERN PH/ED)
READ HWADD ‘i-1’
- - -
READ HWADD ‘0’
*END*
Cardio Test
Which cards are respondingto basic register access?
READ HWADD ‘1’
READ HWADD ‘i’
JUMP
RPINC
CHRDO (Readout)
IF_TRIGGER (L1)
Test Beam Mode
From ALTROs to DAQw/ external L1-trigger:
• ADC sampled data• Pattern stimuli
JUMP
Examples of Instruction Sequences
17/05/04 ALICE TPC Meeting Bernardo Mota (CERN PH/ED)
Pedestal Memory Test
*END*
PMREAD
PMWRITE
Checking ALTRO Pedestalmemory access in a fast way
Read Error register formismatch error
Examples of Instruction Sequences
17/05/04 ALICE TPC Meeting Bernardo Mota (CERN PH/ED)
Current Configuration Paths
ParameterExtraction ALTRO/BC/RCU
parameters
ParameterDatabase
Data BlockAssembler
FE
CF
EC
FE
CF
EC
RCU
Raw DataSoftware Hardware
‘N’ configurationblocks
Transporterto DAQscripts
Transporterto DCSscripts
buffer
buffer
17/05/04 ALICE TPC Meeting Bernardo Mota (CERN PH/ED)
Configuration and Readout TimeF
EC
FE
C
Transporterto DAQscripts
Transporterto DCSscripts
RCU FE
CF
EC
buffer
buffer
Overall configuration data: 7MByte/RCU - Worst case scenario:
• 3200 active channels• 1000 samples/channel 0.7s<1s
Bothpaths
3s
Readout: 3ms
17/05/04 ALICE TPC Meeting Bernardo Mota (CERN PH/ED)
Active Channel / FEC List
Improving readout efficiencyby storing the currentstatus of one channel or board
16bit = 1 ALTRO chip
1: Good0: Non-working
256
wor
ds
ActiveChannel
ListChannel not workingwill not be readout
Active FEC List
32bit = max number of FEC / RCU
Updated by Slow control
17/05/04 ALICE TPC Meeting Bernardo Mota (CERN PH/ED)
Current Trigger and Clock Distribution
RCUboard
PC TT
C V
X
TT
C V
I
P
roc
& P
CI-
VM
E
VME crate
ethernet
CO
RB
O M
odul
e
TriggerInput
• Clock• L1-trigger• Trig.Messages TTC chip
DCS board
FPGA
busy signal
10MHz
40MHz
17/05/04 ALICE TPC Meeting Bernardo Mota (CERN PH/ED)
Operation in High Trigger Rate
4.7KHz Event Rate 80MByte/s
Conditions:
• 100 samples/channel• 128 channels• 40MHz Readout clk• 10MHz Sampling clk
Exercise of full Readout Chainwas performed successfully atKHz range trigger
17/05/04 ALICE TPC Meeting Bernardo Mota (CERN PH/ED)
Present Status
RCU Development
System fully tested and operational:
• 2 branches (12 + 13 frontend cards) in a total of 3200 channels• DCS board running Linux on ARM processor and Ethernet link (Torsten Alt talk)• DAQ with both DATE system and lower level script language for config.• Communication between RCU and HLT fully operational• Installed in the T10 Area, ready for beam (Roberto Campagnolo talk)
ALTRO Configuration tested using both the DCS board and the DDL link√
√
Improvement in readout time by a factor of 2: Replication of readout logic?
Configuration of the RCU firmware from the DCS Board close to completion√
Slow Control through I2C fully operational measuring To, Currents and Voltages(Carmen Gonzalez Gutierrez talk)
√
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