CEC 220 Digital Circuit Design Mealy and Moore State Machines Friday, March 27 CEC 220 Digital...

CEC 220 Digital Circuit DesignMealy and Moore State Machines

Friday, March 27 CEC 220 Digital Circuit Design Slide 1 of 16

Lecture Outline

Friday, March 27 CEC 220 Digital Circuit Design

• Design of a Sequence Detector• Guidelines for Construction of State Graphs

Slide 2 of 16

Mealy and Moore State MachinesDesign of a Sequence Detector

Friday, March 27 CEC 220 Digital Circuit Design

• Design a “state machine” to detect two or more 1’s in a row on a clocked input A sequence detector Assert the output ‘Z’ if correct sequence is detected

…,0,1,1,0,0,…State

Machinew z

Clk

Slide 3 of 16

Mealy and Moore State MachinesDesign of a Sequence Detector

Friday, March 27 CEC 220 Digital Circuit Design

• Design a “state machine” to detect two or more 1’s in a row on a clocked input

S0z=0

S1z=0

S11z=1

RESET w=1

w=0w=0

w=1

w=1

w=0

State Name

Output

Legend:

State Transitions ONLY occur when the clock “ticks”

Input = ?

Slide 4 of 16

Mealy and Moore State MachinesDesign of a Sequence Detector – Moore Design

Friday, March 27 CEC 220 Digital Circuit Design

• State Transition Table

Present State

Next State Present Output (Z)w=0 w=1

S0z=0

S1z=0

S11z=1

RESET w=1

w=0w=0

w=1

w=0

S0 0S0 S1S1 0S0 S11

S11 1S0 S11

Present State

Next State Present Output (Z)w=0 w=1

00011011

Present State

Next State Present Output (Z)w=0 w=1

00 00 01 001 00 10 010 00 10 111 XX XX X

QAQB

S0 = 00S1 = 01

S11 = 10

State Encodings

How many FFs will we need?

Slide 5 of 16

0 1

0

1

Mealy and Moore State MachinesDesign of a Sequence Detector – Moore Design

Friday, March 27 CEC 220 Digital Circuit Design

• Circuit Design Let’s use D-type FFs

0 1

00

01

11

10

0 1

00

01

11

10

PresentState

Next State Present Output (Z)w=0 w=1

00 00 01 001 00 10 010 00 10 111 XX XX X

0 1

00 0 0

01 0 1

11 X X

10 0 1

𝑄𝐴𝑄𝐵𝑤𝐷 𝐴

0 1

00 0 1

01 0 0

11 X X

10 0 0

𝑄𝐴𝑄𝐵𝑤𝐷𝐵

B A BD wQ Q A B AD w Q Q

AZ Q

0 1

0 0 1

1 0 X

𝑄𝐵

𝑄𝐴𝑍

Slide 6 of 16

Mealy and Moore State MachinesDesign of a Sequence Detector – Moore Design

Friday, March 27 CEC 220 Digital Circuit Design

• Circuit Design A B AD w Q Q B A BD wQ Q

Clk

w

AZ Q

Z

Input Logic Flip-Flops Output Logic

Output is a function of ONLY the current state

Slide 7 of 16

Mealy and Moore State MachinesDesign of a Sequence Detector – Moore Design

Friday, March 27 CEC 220 Digital Circuit Design

• Architecture of a Moore State Machine Outputs are a function of only the current state

Flip-Flops

Q’s

Clock

FF InputsInput Combinational

Logic

State of FFs

Inpu

ts

Output Combinational

Logic

Out

puts

Slide 8 of 16

Mealy and Moore State MachinesDesign of a Sequence Detector – Mealy Design

Friday, March 27 CEC 220 Digital Circuit Design

• Design a “state machine” to detect two or more 1’s in a row on a clocked input Now we will allow the state machine’s output to change asynchronously!!

o i.e., NOT synchronized with the clock

S0

S1

RESET w=0 / z=0

w=1 / z=0

w=0

/ z=

0

w=1 / z=1

State Name

Legend:

State Transitions ONLY occur when the clock “ticks”

Input = ? /

Output = ?

Slide 9 of 16

Mealy and Moore State MachinesDesign of a Sequence Detector – Mealy Design

Friday, March 27 CEC 220 Digital Circuit Design

• State Transition Table

S0

S1

RESET w=0 / z=0

w=1 / z=0

w=0

/ z=

0

w=1 / z=1

QA

S0 = 0S1 = 1

State Encodings

How many FFs will we need?

Present State

Next State Present Output (Z)w=0 w=1 w=0 w=1

S0 S0 0 0S1S1 S0 0 1S1

Present State

Next State Present Output (Z)w=0 w=1 w=0 w=1

0 0 01 0 1

Present State

Next State Present Output (Z)w=0 w=1 w=0 w=1

0 0 1 0 01 0 1 0 1

Slide 10 of 16

Mealy and Moore State MachinesDesign of a Sequence Detector – Mealy Design

Friday, March 27 CEC 220 Digital Circuit Design

• Circuit Design Let’s use D-type FFs

Present State

Next State Present Output (Z)w=0 w=1 w=0 w=1

0 0 1 0 01 0 1 0 1

0 1

0

1

0 1

0 0 1

1 0 1

𝑄𝐴𝑤𝐷 𝐴

AD w

0 1

0

1

0 1

0 0 0

1 0 1

𝑄𝐴𝑤𝑍

AZ wQ

Slide 11 of 16

Mealy and Moore State MachinesDesign of a Sequence Detector – Mealy Design

Friday, March 27 CEC 220 Digital Circuit Design

• Circuit Design

Clk

w

Input Logic Flip-Flops Output Logic

AD w AZ wQ

Z Output is a function of the current state and the input

Output no longer synchronized with the clock

Slide 12 of 16

Mealy and Moore State MachinesDesign of a Sequence Detector – Mealy Design

Friday, March 27 CEC 220 Digital Circuit Design

• Architecture of a Mealy State Machine Outputs are now a function of the current state and the input

Flip-Flops

Q’s

Clock

FF InputsInput Combinational

Logic

State of FFs

Inpu

ts

Output Combinational

Logic

Out

puts

Slide 13 of 16

S0z=0

S1z=0

S11z=1

RESET w=1

w=0w=0

w=1

w=0

Mealy and Moore State MachinesDesign of a Sequence Detector

Friday, March 27 CEC 220 Digital Circuit Design

• Comparing the Mealy and Moore Designs

Clk

w Z

Moore State Machine Mealy State Machine

0 1 0 1 1 0

Slide 14 of 16

S0

S1

RESET w=0 / z=0

w=1 / z=0

w=0

/ z=

0

w=1 / z=1

Clk

w Z

???

Friday, March 27 CEC 220 Digital Circuit Design

• Comparing Mealy and Moore State Machines

Moore State Machine Mealy State Machine

• States change on the clock edge

• Output is only a function of the current state

• Output changes are synchronized with the clock

• Typically, more states than a Mealy machine

• States change on the clock edge

• Output is a function of the current state and the current input

• Output changes are NOT synchronized with the clock

• Typically, fewer states than a Moore machine

Mealy machines can produce false outputs

Mealy machines outputs are only valid immediately preceding clock edges!!

Slide 15 of 16

Next Lecture

Friday, March 27 CEC 220 Digital Circuit Design

• Analysis from Timing Diagrams Reverse engineering

• Analysis from Circuit Diagrams Reverse engineering

Slide 16 of 16