Chapter 3 Digital Logic Structures

Chapter 3Digital LogicStructures

3-2

Basic Logic Gates

Basic Relations of Boolean Algebra

x + 0 = xx + 1 = 1x + x = xx + x’ = 1x + y = y + x (Commutative)x + (y+z) = (x+y)+z (Associative)x(y+z’) = xy + xz (Distributive)(x+y)’ = x’ y’ (DeMorgan)(x’)’ = x

x0 = 0x1 = xxx = xxx’ = 0xy = yx (Commutative)x(yz) = (xy)z (Associative)x+yz = (x+y)(x+z) (Distributive)(xy)’ = x’+y’ (DeMorgan)

3-3

+ = OR= AND‘ = NOT

DeMorgan’s Law

3-4

not(A and B) = (not A) or (not B)

not(A or B) = (not A) and (not B)

A and B A or B =

A or B A and B =

3-5

More than 2 Inputs?AND/OR can take any number of inputs.

• AND = 1 if all inputs are 1.• OR = 1 if any input is 1.• Similar for NAND/NOR.

Can implement with multiple two-input gates,or with single CMOS circuit.

3-6

SummaryMOS transistors are used as switches to implementlogic functions.

• n-type: connect to GND, turn on (with 1) to pull down to 0• p-type: connect to +2.9V, turn on (with 0) to pull up to 1

Basic gates: NOT, NOR, NAND• Logic functions are usually expressed with AND, OR, and NOT

DeMorgan's Law• Convert AND to OR (and vice versa)

by inverting inputs and output

3-7

Building Functions from Logic GatesCombinational Logic Circuit

• output depends only on the current inputs• stateless

Sequential Logic Circuit• output depends on the sequence of inputs (past and present)• stores information (state) from past inputs

We'll first look at some useful combinational circuits,then show how to use sequential circuits to store information.

3-8

Decodern inputs, 2n outputs

• exactly one output is 1 for each possible input pattern

2-bitdecoder

3-9

Multiplexer (MUX)n-bit selector and 2n inputs, one output

• output equals one of the inputs, depending on selector

4-to-1 MUX

Mux (cont.)

3-10

• In general, a MUX has2n data inputsn select (or control) linesand 1 output.

• It behaves like a channel selector.

A 4-to-1 MUX: Out takes the value of A,B, C or Ddepending on the value of S (00, 01, 10, 11)

S[1:0]

A B C D

Out

.S D.S S. C.S .S SB. S. SA. Out 10101010

A B C D

Out

S0

S1

Adder

3-11

Half Adder• 2 inputs• 2 outputs: sum and carry

Full Adder• performs the addition in column i• 3 inputs: ai, bi and ci

• 2 outputs: si and ci+1

• ci is the carry in from bit position i-1• ci+1 is the carry out to bit position i+1

ai bi ci+1 si0 0 0 00 1 0 11 0 0 11 1 1 0

Half-adder truth table

n 1 n 2 1 0

n 1 n 2 1 0

n 1 n 2 1

n 1 n 2 1 0

a a ... a a b b ... b b

c c ... c 0

s s ... s s

3-12

Full AdderAdd two bits and carry-in,produce one-bit sum and carry-out. A B Cin S Cout

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

Full Adder (cont)

3-13

).(.1 iiiiii

iiii

bacbaccbas

where

operation OR theis operation AND theis .

OR exclusive is

- verify that this corresponds to the gate-level implementation.

3-14

Four-bit Adder

1010 Cin

0101 A+ 1101 B10010 S

3-15

Logical CompletenessCan implement ANY truth table with AND, OR, NOT.

A B C D0 0 0 00 0 1 0

0 1 0 1

0 1 1 0

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 0

1. AND combinations that yield a "1" in the truth table.

2. OR the resultsof the AND gates.