Digital Integrated CircuitsDigital Integrated Circuits Introduction: Issues in digital design The CMOS inverter Combinational logic structures Sequential logic gates Design methodologies Interconnect: R, L and C Timing Arithmetic building blocks Memories and array structures

IntroductionIntroduction

Why is designing digital ICs different today than it was before?

Will it change in future?

Moore’s LawMoore’s Law

In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months

Moore’s LawMoore’s Law

161514131211109876543210

195

9

196

0

196

1

196

2

196

3

196

4

196

5

196

6

196

7

196

8

196

9

197

0

197

1

197

2

197

3

197

4

197

5

LO

G 2 O

F T

HE

NU

MB

ER

OF

CO

MP

ON

EN

TS

PE

R I

NT

EG

RA

TE

D F

UN

CT

ION

Electronics, April 19, 1965.

Evolution in ComplexityEvolution in Complexity

Transistor CountsTransistor Counts

1,000,000

100,000

10,000

1,000

10

100

11975 1980 1985 1990 1995 2000 2005 2010

8086

80286i386

i486Pentium®

Pentium® Pro

K1 Billion 1 Billion

TransistorsTransistors

Source: IntelSource: Intel

ProjectedProjected

Pentium® IIPentium® III

Courtesy, Intel

Moore’s law in MicroprocessorsMoore’s law in Microprocessors

40048008

80808085 8086

286386

486Pentium® proc

P6

0.001

0.01

0.1

1

10

100

1000

1970 1980 1990 2000 2010Year

Tra

nsi

sto

rs (

MT

)

2X growth in 1.96 years!

Transistors on Lead Microprocessors double every 2 yearsTransistors on Lead Microprocessors double every 2 years

Courtesy, Intel

Die Size GrowthDie Size Growth

40048008

80808085

8086286

386486 Pentium ® proc

P6

1

10

100

1970 1980 1990 2000 2010Year

Die

siz

e (m

m)

~7% growth per year~2X growth in 10 years

Die size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s Law

Courtesy, Intel

FrequencyFrequency

P6Pentium ® proc

486386

28680868085

8080

80084004

0.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Fre

qu

ency

(M

hz)

Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 years

Doubles every2 years

Courtesy, Intel

Power DissipationPower Dissipation

P6Pentium ® proc

486

3862868086

80858080

80084004

0.1

1

10

100

1971 1974 1978 1985 1992 2000Year

Po

wer

(W

atts

)

Lead Microprocessors power continues to increaseLead Microprocessors power continues to increase

Courtesy, Intel

Power will be a major problemPower will be a major problem

5KW 18KW

1.5KW 500W

40048008

80808085

8086286

386486

Pentium® proc

0.1

1

10

100

1000

10000

100000

1971 1974 1978 1985 1992 2000 2004 2008Year

Po

wer

(W

atts

)

Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive

Courtesy, Intel

Power densityPower density

400480088080

8085

8086

286386

486Pentium® proc

P6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Po

wer

Den

sity

(W

/cm

2)

Hot Plate

NuclearReactor

RocketNozzle

Power density too high to keep junctions at low tempPower density too high to keep junctions at low temp

Courtesy, Intel

Not Only MicroprocessorsNot Only Microprocessors

Digital Cellular Market(Phones Shipped)

1996 1997 1998 1999 2000

Units 48M 86M 162M 260M 435M Analog Baseband

Digital Baseband

(DSP + MCU)

PowerManagement

Small Signal RF

PowerRF

(data from Texas Instruments)(data from Texas Instruments)

CellPhone

Challenges in Digital DesignChallenges in Digital Design

“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation• Clock distribution.

Everything Looks a Little Different

“Macroscopic Issues”• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability• etc.

…and There’s a Lot of Them!

DSM 1/DSM

?

Productivity TrendsProductivity Trends

1

10

100

1,000

10,000

100,000

1,000,000

10,000,000

200

3

198

1

198

3

198

5

198

7

198

9

199

1

199

3

199

5

199

7

199

9

200

1

200

5

200

7

200

9

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

Logic Tr./ChipTr./Staff Month.

xxx

xxx

x

21%/Yr. compoundProductivity growth rate

x

58%/Yr. compoundedComplexity growth rate

10,000

1,000

100

10

1

0.1

0.01

0.001

Lo

gic

Tra

nsi

sto

r p

er C

hip

(M)

0.01

0.1

1

10

100

1,000

10,000

100,000

Pro

du

ctiv

ity

(K)

Tra

ns.

/Sta

ff -

Mo

.

Source: Sematech

Complexity outpaces design productivity

Co

mp

lexi

ty

Courtesy, ITRS Roadmap

Why Scaling?Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more

functions per chip; chip cost does not increase significantly

Cost of a function decreases by 2x But …

How to design chips with more and more functions? Design engineering population does not double every

two years… Hence, a need for more efficient design methods

Exploit different levels of abstraction

Design Abstraction LevelsDesign Abstraction Levels

n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

Design MetricsDesign Metrics

How to evaluate performance of a digital circuit (gate, block, …)? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function

Cost of Integrated CircuitsCost of Integrated Circuits

NRE (non-recurrent engineering) costs design time and effort, mask generation one-time cost factor

Recurrent costs silicon processing, packaging, test proportional to volume proportional to chip area

NRE Cost is IncreasingNRE Cost is Increasing

Die CostDie Cost

Single die

Wafer

From http://www.amd.com

Going up to 12” (30cm)

Cost per TransistorCost per Transistor

0.00000010.0000001

0.0000010.000001

0.000010.00001

0.00010.0001

0.0010.001

0.010.01

0.10.111

19821982 19851985 19881988 19911991 19941994 19971997 20002000 20032003 20062006 20092009 20122012

cost: cost: ¢-per-¢-per-transistortransistor

Fabrication capital cost per transistor (Moore’s law)

YieldYield%100

per wafer chips ofnumber Total

per wafer chips good of No.Y

yield Dieper wafer Dies

costWafer cost Die

area die2

diameterwafer

area die

diameter/2wafer per wafer Dies

2

DefectsDefects

area dieareaunit per defects

1yield die

is approximately 3

4area) (die cost die f

Some Examples (1994)Some Examples (1994)Chip Metal

layersLine width

Wafer cost

Def./ cm2

Area mm2

Dies/wafer

Yield Die cost

386DX 2 0.90 $900 1.0 43 360 71% $4

486 DX2 3 0.80 $1200 1.0 81 181 54% $12

Power PC 601

4 0.80 $1700 1.3 121 115 28% $53

HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73

DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149

Super Sparc 3 0.70 $1700 1.6 256 48 13% $272

Pentium 3 0.80 $1500 1.5 296 40 9% $417

Reliability―Reliability―Noise in Digital Integrated CircuitsNoise in Digital Integrated Circuits

i(t)

Inductive coupling Capacitive coupling Power and ground noise

v(t) VDD

DC OperationDC OperationVoltage Transfer CharacteristicVoltage Transfer Characteristic

V(x)

V(y)

VOH

VOL

VM

VOH

VOL

fV(y)=V(x)

Switching Threshold

Nominal Voltage Levels

VOH = f(VOL)VOL = f(VOH)VM = f(VM)

Mapping between analog and digital signalsMapping between analog and digital signals

VIL

VIH

Vin

Slope = -1

Slope = -1

VOL

VOH

Vout

“ 0” VOL

VIL

VIH

VOH

UndefinedRegion

“ 1”

Definition of Noise MarginsDefinition of Noise Margins

Noise margin high

Noise margin low

VIH

VIL

UndefinedRegion

"1"

"0"

VOH

VOL

NMH

NML

Gate Output Gate Input

Noise BudgetNoise Budget

Allocates gross noise margin to expected sources of noise

Sources: supply noise, cross talk, interference, offset

Differentiate between fixed and proportional noise sources

Key Reliability PropertiesKey Reliability Properties

Absolute noise margin values are deceptive a floating node is more easily disturbed than a

node driven by a low impedance (in terms of voltage)

Noise immunity is the more important metric – the capability to suppress noise sources

Key metrics: Noise transfer functions, Output impedance of the driver and input impedance of the receiver;

Regenerative PropertyRegenerative Property

v0

v1

v3

finv(v)

f(v)

v3

out

v

Regenerative Non-Regenerativev2

v1

f(v)

finv(v)

v3

out

v

Regenerative PropertyRegenerative Property

A chain of inverters

v0 v1 v2 v3 v4 v5 v6

2

V (

Volt

)

4

v0

v1v2

t (nsec)0

2 1

1

3

5

6 8 10 Simulated response

Fan-in and Fan-outFan-in and Fan-out

N

Fan-out N Fan-in M

M

The Ideal GateThe Ideal Gate

Ri = Ro = 0Fanout = NMH = NML = VDD/2 g =

V in

V out

An Old-time InverterAn Old-time Inverter

NMH

Vin (V)

NM L

VM

0.0

1.0

2.0

3.0

4.0

5.0

1.0 2.0 3.0 4.0 5.0

Delay DefinitionsDelay Definitions

Vout

tf

tpHL tpLH

tr

t

Vin

t

90%

10%

50%

50%

Ring OscillatorRing Oscillator

v0 v1 v5

v1 v2v0 v3 v4 v5

T = 2 tp N

A First-Order RC NetworkA First-Order RC Network

vout

vin C

R

tp = ln (2) = 0.69 RC

Important model – matches delay of inverter

Power DissipationPower Dissipation

Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t)

Peak power: Ppeak = Vsupplyipeak

Average power:

Tt

t

Tt

t supplysupply

ave dttiT

Vdttp

TP )(

1

Energy and Energy-DelayEnergy and Energy-Delay

Power-Delay Product (PDP) =

E = Energy per operation = Pav tp

Energy-Delay Product (EDP) =

quality metric of gate = E tp

A First-Order RC NetworkA First-Order RC NetworkVdd

Vout

isupply

CL

E0->1 = CLVdd2

PMOS

NETWORK

NMOS

A1

AN

NETWORK

E0 1 P t dt0

T Vdd isupply t dt

0

T Vdd CLdVout

0

Vdd

CL Vdd 2= = = =

Ecap Pcap t dt0

T Vouticap t dt

0

T CLVoutdVout

0

Vdd 1

2---C

LVdd

2= = = =

vout

vin CL

R

SummarySummary Digital integrated circuits have come a long

way and still have quite some potential left for the coming decades

Some interesting challenges ahead Getting a clear perspective on the challenges and

potential solutions is the purpose of this book Understanding the design metrics that govern

digital design is crucial Cost, reliability, speed, power and energy

dissipation