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Computer Organization and Design Building a Computer!. Montek Singh Fri, Nov 15, 2013 Lecture 14. Building a Computer. A. Instruction. A. B. Memory. D. ALU. 1. 0. THIS IS IT! We are now ready to build a computer. The ingredients are all in place, so let ’ s put them together…. - PowerPoint PPT Presentation
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Computer Organization and Computer Organization and DesignDesign
Building a Computer!Building a Computer!
Montek SinghMontek SinghFri, Nov 15, 2013Fri, Nov 15, 2013
Lecture 14Lecture 14
Building a ComputerBuilding a ComputerTHIS IS IT!THIS IS IT!
We are now ready to We are now ready to build a computer.build a computer.
The ingredients are The ingredients are all in place, so let’s all in place, so let’s put them together…put them together…
I wonder wherethis goes?
Instruction
Memory
A
D
0
1
MIPS Kit
ALU
A
B
Datapath and ControlDatapath and Control DatapathDatapath
Consists of all of those components that store or Consists of all of those components that store or process dataprocess data
Registers, ALU, memoriesRegisters, ALU, memories ControlControl
Consists of those components that tell datapath Consists of those components that tell datapath components what to do and whencomponents what to do and when
Clock, control logic (finite state machines or Clock, control logic (finite state machines or combinational look-up tables)combinational look-up tables)
Datapath for R-type InstructionsDatapath for R-type Instructions Registers and ALURegisters and ALU
All of the registers together are called register bank, All of the registers together are called register bank, or “register file”or “register file”
Read Reg. 1 (rs)5
5
5
32
Read Reg. 2 (rt)
Write Reg. (rd)
Write Data
data 1
data 2
3
ALU Operation
Inst Bits 25-21
Inst Bits 20-16
Inst Bits 15-11
RegWrite (1 means write, 0 means don’t)
32
32
ALU
Register FileRegister File 32 registers ($0-$31), each 32 bits wide32 registers ($0-$31), each 32 bits wide 2 ports for reading, 1 port for writing2 ports for reading, 1 port for writing
Register 0
Register 1
Register 2
Register 3
Register 4
Register ...
Register 30
Register 31
32 to1 MUX
Read Reg 1
Data 1
There are 32 bits in each register!
LOT’S OF CONNECTIONS!
And this is just one port! Remember, there’s data1 and data2 coming out of the register file!
5
32
Register File has 3 portsRegister File has 3 ports
Read Reg. 15
5
5
32
Read Reg. 2
Write Reg.
Write Data
data 1
data 2
Inst Bits 25-21
Inst Bits 20-16
Inst Bits 15-11
RegWrite
32
32
2 Read Ports
1 Write PortREALLY LOTS OF CONNECTIONS!
This is one reason we have only a small number of registers
What’s another reason?
Let’s review our ALULet’s review our ALU Let’s review the ALU that we built a few Let’s review the ALU that we built a few
lectures ago.lectures ago.
Sub Bool Shft Math OP 0 XX 0 1 A+B 1 XX 0 1 A-B X 00 1 0 B<<A X 10 1 0 B>>A X 11 1 0 B>>>A X 00 0 0 A & B X 01 0 0 A | B X 10 0 0 A ^ B X 11 0 0 A | B
5-bit ALUFN
FlagsN,V,C
A B
Result
BidirectionalShifter BooleanAdd/SubSub
BoolShft
Math
1 0
1 0
ZFlag
A minor modification to our ALUA minor modification to our ALU Here’s that ALU Here’s that ALU with a minor modification to support with a minor modification to support
comparisonscomparisons
Sub Bool Shft Math OP 0 XX 0 1 A+B 1 XX 0 1 A-B 1 X0 1 1 A LT B 1 X1 1 1 A LTU B X 00 1 0 B<<A X 10 1 0 B>>A X 11 1 0 B>>>A X 00 0 0 A & B X 01 0 0 A | B X 10 0 0 A ^ B X 11 0 0 A | B
5-bit ALUFN
FlagsN,V,C
A B
Result
BidirectionalShifter BooleanAdd/SubSub
Bool
ShftMath
1 0
1 0
ZFlag
0 1
<?
Design ApproachDesign Approach““Incremental FeaturismIncremental Featurism””
We will implement circuits for each type of We will implement circuits for each type of instruction individually, and merge them (using instruction individually, and merge them (using MUXes, etc).MUXes, etc).
Our Bag of Components:
Registers0 1 Muxes
ALUA B ALU & adders
DataMemory
WD
A
RD
R/W
RegisterFile
(3-port)
RA1 RA2
WA
WE
WD
RD1 RD2
InstructionMemory
A
D
Memories
+
Steps:Steps: 1. 3-Operand ALU instrs1. 3-Operand ALU instrs 2. ALU w/immediate instrs2. ALU w/immediate instrs 2. Loads & Stores2. Loads & Stores 3. Jumps & Branches 3. Jumps & Branches 4. Exceptions (briefly)4. Exceptions (briefly)
Review: The MIPS ISAReview: The MIPS ISA
Instruction classesdistinguished by types:1) 3-operand ALU2) ALU w/immediate3) Loads/Stores4) Branches5) Jumps
The MIPS instruction set as seen from a Hardware Perspective
OP 6 5 5 5 5 6
1626
000000 rs rt rd funcshamtR-type: ALU with Register operands
Reg[rd] Reg[rs] op Reg[rt]001XXX rs rt
immediate
I-type: ALU with constant operandReg[rt] Reg[rs] op SEXT(immediate)
10X011 rs rtimmediate
I-type: Load and StoreReg[rt] Mem[Reg[rs] + SEXT(immediate)]Mem[Reg[rs] + SEXT(immediate)] Reg[rt]
I-type: Branch Instructionsif (Reg[rs] == Reg[rt]) PC PC + 4 + 4*SEXT(immediate) if (Reg[rs] != Reg[rt]) PC PC + 4 + 4*SEXT(immediate)
10X011 immediaters rt
00001X 26-bit constant J-type: jump
PC (PC & 0xf0000000) | 4*(immediate)
Fetching Sequential InstructionsFetching Sequential Instructions
PC
4
We will talk about branches and jumps later.
flipflop
+32
32
ReadAddress Instruction
InstructionMemory
32
32
Instruction Fetch/DecodeInstruction Fetch/Decode Use a counter to FETCH Use a counter to FETCH
the next instruction:the next instruction: PROGRAM COUNTER (PC)PROGRAM COUNTER (PC)
use PC as memory use PC as memory addressaddress
add 4 to PC, load new add 4 to PC, load new value at end of cyclevalue at end of cycle
fetch instruction from fetch instruction from memorymemory use some instruction use some instruction
fields directly (register fields directly (register numbers, 16-bit numbers, 16-bit constant)constant)
decode rest of the decode rest of the instructioninstruction use bits <31:26> and use bits <31:26> and
<5:0> to generate <5:0> to generate controlscontrols
INSTRUCTIONWORDFIELDS
PC
+4
InstructionMemor
y
A
D
Control Logic
CONTROL SIGNALS
00
OP[31:26], FUNC[5:0]
32
32
32
3-Operand ALU Data Path3-Operand ALU Data Path
RegisterFile
RA1 RA2
RD1 RD2WA WD
WE
Rd: <15:11>
PC
+4
InstructionMemory
A
D
Rt: <20:16>
ALUA B
ALUFN
Control Logic
WERF
ALUFN
WERF
00
32 32
32
Rs: <25:21>
000000 rs rt rd 100XXX00000
R-type: ALU with Register operands Reg[rd] Reg[rs] op Reg[rt]
WERF!
Shift InstructionsShift Instructions
RegisterFile
RA1 RA2
RD1 RD2WA WD
WE
Rd: <15:11>
PC
+4
InstructionMemory
A
D
Rt: <20:16>
ALUA B
ALUFN
Control Logic
WERF
ALUFN
WERF
00
32
000000 rs rt rd 000XXXshamt
R-type: ALU with Register operands sll: Reg[rd] Reg[rt] (shift) shamtsllv: Reg[rd] Reg[rt] (shift) Reg[rs]
ASEL
Rs: <25:21>
ASEL10
shamt:<10:6>
ASEL!
ALU with ImmediateALU with Immediate
WA
PC
+4
InstructionMemory
A
D
Rt: <20:16>
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WDWE
ALUFN
Control Logic
ALUFN
BSEL01
imm: <15:0>
BSEL
WERF
WERF
00
BSEL!
001XXX rs rtimmediat
eI-type: ALU with constant operand
Reg[rt] Reg[rs] op SEXT(immediate)
Rd:<15:11>Rt:<20:16>
0
1
SEXTSEXT
SEXT
ASEL
BSELRs: <25:21>
ASEL10
shamt:<10:6>
How do you build SEXT?•1 pad with sign•0 pad with 0s
Load InstructionLoad Instruction
WA
PC
+4
InstructionMemory
A
D
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WDWE
ALUFN
Control Logic
Imm: <15:0>
Data MemoryRD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSELALUFNWr
WERF
WERF
00
32
32
Rd:<15:11>Rt:<20:16>
0
1
BSEL
SEXT
100011 rs rtimmediat
eI-type: Load
Reg[rt] Mem[Reg[rs] + SEXT(immediate)]
ASEL
Rt: <20:16>Rs: <25:21>
SEXT
BSEL01
SEXT
ASEL10
shamt:<10:6>
Store InstructionStore Instruction
WA
PC
+4
InstructionMemory
A
D
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WDWE
ALUFN
Control Logic
Imm: <15:0>
Data MemoryRD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSELALUFNWr
WERF
WERF
00
32
Rd:<15:11>Rt:<20:16>
0
1
SEXT
ASEL
10X011 rs rtimmediat
eI-type: Store
Mem[Reg[rs] + SEXT(immediate)] Reg[rt]
Rt: <20:16>BSEL
No WERF!
Rs: <25:21>
ASEL10
SEXT
BSEL01
SEXT
shamt:<10:6>
JMP InstructionsJMP Instructions
WA
PC
+4
InstructionMemory
A
D
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WDWE
ALUFN
Control Logic
Data MemoryRD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSELALUFNWr
J:<25:0>
PCSEL
WERF
WERF
00
32PC+4
Rt: <20:16>
Imm: <15:0>
ASEL
SEXT
00001X 26-bit constant J-type: j: PC (PC & 0xf0000000) | 4*(immediate) jal: PC (PC & 0xf0000000) | 4*(immediate);
Reg[31] PC + 4
PC<31:28>:J<25:0>:00
WASEL
Rs: <25:21>
ASEL10
SEXT
BSEL01
SEXT
shamt:<10:6>
PCSEL 0123456
WASEL
Rd:<15:11>Rt:<20:16> 0
1231
BEQ/BNE InstructionsBEQ/BNE Instructions
WA
PC
+4
InstructionMemory
A
D
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WDWE
ALUFN
Control Logic
Data MemoryRD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSELALUFNWr
J:<25:0>
PCSEL
WERF
WERF
00
32PC+4
Rt: <20:16>
Imm: <15:0>
ASEL
SEXT
10X011 immediaters rt
R-type: Branch Instructionsif (Reg[rs] == Reg[rt]) PC PC + 4 + 4*SEXT(immediate)if (Reg[rs] != Reg[rt]) PC PC + 4 + 4*SEXT(immediate)
+x4
BT
Z
Z
BTPC<31:28>:J<25:0>:00
Why add, another adder? Couldn’t we reuse the one in the ALU? Nope, it needs to do a subtraction.
That “x4” unit is trivial. I’ll just wire the input shifted over 2–bit positions.
WASEL
Rs: <25:21>
ASEL10
SEXT
BSEL01
SEXT
shamt:<10:6>
PCSEL 0123456
WASEL
Rd:<15:11>Rt:<20:16>
31
012
Jump Indirect InstructionsJump Indirect Instructions
WA
PC
+4
InstructionMemory
A
D
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WDWE
ALUFN
Control Logic
Data MemoryRD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSELALUFNWr
J:<25:0>
PCSEL
WERF
WERF
00
32PC+4
Rt: <20:16>
Imm: <15:0>
ASEL
SEXT
R-type: Jump Indirect, Jump and Link Indirectjr: PC Reg[rs]jalr: PC Reg[rs], Reg[rd] PC + 4
Z
Z
BT
WASEL
PC<31:28>:J<25:0>:00
000000 rs rt rd 00100X00000
JT
JT
Rs: <25:21>
ASEL10
SEXT
BSEL01
SEXT
shamt:<10:6>
PCSEL 0123456
WASEL
Rd:<15:11>Rt:<20:16>
31
012
BT
+x4
ComparisonsComparisons
WA
PC
+4
InstructionMemory
A
D
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WDWE
ALUFN
Control Logic
Data MemoryRD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSELALUFNWr
J:<25:0>
PCSEL
WERF
WERF
00
32PC+4
Rt: <20:16>
Imm: <15:0>
ASEL
SEXT
I-type: set on less than & set on less than unsigned immediate slti: if (Reg[rs] < SEXT(imm)) Reg[rt] 1; else Reg[rt] 0 sltiu: if (Reg[rs] < SEXT(imm)) Reg[rt] 1; else Reg[rt] 0
Z
Z
BT
WASEL
PC<31:28>:J<25:0>:00
JT
JT 001XXX immediat
ers rt
Reminder:To evaluate (A < B) we first compute A-B and look at the flags.
LT = N V LTU = C
Rs: <25:21>
ASEL10
SEXT
BSEL01
SEXT
shamt:<10:6>
PCSEL 0123456
Rd:<15:11>Rt:<20:16>
WASEL
31
012
BT
+x4
More comparisonsMore comparisons
WA
PC
+4
InstructionMemory
A
D
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WDWE
ALUFN
Control Logic
Data MemoryRD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSELALUFNWr
J:<25:0>
PCSEL
WERF
WERF
00
32PC+4
Rt: <20:16>
Imm: <15:0>
ASEL
SEXT
R-type: set on less than & set on less than unsigned slt: if (Reg[rs] < Reg[rt]) Reg[rd] 1; else Reg[rd] 0 sltu: if (Reg[rs] < Reg[rt]) Reg[rd] 1; else Reg[rd] 0
Z
BT
WASEL
PC<31:28>:J<25:0>:00
JT
JT 000000 rs rt rd 10101X00000
Z
Rs: <25:21>
ASEL10
SEXT
BSEL01
SEXT
shamt:<10:6>
PCSEL 0123456
Rd:<15:11>Rt:<20:16>
BT
+x4
WASEL
31
012
LUILUI
WA
PC
+4
InstructionMemory
A
D
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WDWE
ALUFN
Control Logic
Data MemoryRD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSELALUFNWr
J:<25:0>
PCSEL
WERF
WERF
00
32PC+4
Rt: <20:16>
Imm: <15:0>
ASEL
SEXT
I-type: Load upper immediate lui: Reg[rt] Immediate << 16
Z
BT
WASEL
PC<31:28>:J<25:0>:00
JT
JT
Z
001XXX immediate00000 rt
Rs: <25:21>
SEXT
BSEL01
SEXT
PCSEL 0123456
Rd:<15:11>Rt:<20:16>
ASEL20
shamt:<10:6>
“16”
1
WASEL
31
012
BT
+x4
Reset, Interrupts, and ExceptionsReset, Interrupts, and Exceptions Upon reset/reboot:Upon reset/reboot:
Need to set PC to where boot code resides in memoryNeed to set PC to where boot code resides in memory Interrupts/Exceptions:Interrupts/Exceptions:
any event that causes interruption in program flowany event that causes interruption in program flow FAULTS: e.g., nonexistent opcode, divide-by-zeroFAULTS: e.g., nonexistent opcode, divide-by-zero TRAPS & system calls: e.g., read-a-characterTRAPS & system calls: e.g., read-a-character I/O events: e.g., key pressedI/O events: e.g., key pressed
How to handle?How to handle? interrupt current running programinterrupt current running program invoke exception handlerinvoke exception handler return to program to continue executionreturn to program to continue execution
Registers $k0, $k1 ($26, $27)Registers $k0, $k1 ($26, $27) reserved for operating system (kernel), interrupt handlersreserved for operating system (kernel), interrupt handlers any others used must be saved/restoredany others used must be saved/restored
ExceptionsExceptions
WA
PC
+4
InstructionMemory
A
D
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WDWE
ALUFN
Control Logic
Data MemoryRD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSELALUFNWr
J:<25:0>
PCSEL
WERF
WERF
00
32PC+4
Rt: <20:16>
Imm: <15:0>
ASEL
SEXT
Z
BT
WASEL
PC<31:28>:J<25:0>:00
JT
JT
Z
Rs: <25:21>
SEXT
BSEL01
SEXT
PCSEL 0123456
LSEL
IRQ
0x800000800x800000400x80000000
RESET
IRQ: Reg[27] PC+4; PC 0x80000080Bad Opcode: Reg[27] PC+4; PC 0x80000040
Reset: PC 0x80000000
ASEL20
shamt:<10:6>
“16”
1
WASEL
Rd:<15:11>Rt:<20:16> 0
123
3127
BT
+x4
MIPS: Our Final VersionMIPS: Our Final VersionThis is a complete 32-bit processor.Although designed in “one” class lecture,it executes the majority of theMIPS R2000 instruction set.
Executes one instruction per clock
WA
PC
+4
InstructionMemory
A
D
RegisterFile
RA1 RA2
RD1 RD2
ALUA B
WA WDWE
ALUFN
Control Logic
Data MemoryRD
WD R/W
Adr
Wr
WDSEL0 1 2
BSELWDSELALUFNWr
J:<25:0>
PCSEL
WERF
WERF
00
PC+4
Rt: <20:16>
Imm: <15:0>
ASEL
SEXT
Z
BT
WASEL
PC<31:28>:J<25:0>:00
JT
JT
Z
Rs: <25:21>
ASEL20
SEXT
BSEL01
SEXT
shamt:<10:6>
PCSEL 0123456
“16”
IRQ
0x800000800x800000400x80000000
RESET
1
BT
+x4
WASEL
Rd:<15:11>Rt:<20:16> 0
123
3127
MIPS ControlMIPS Control The control unit can be built as a large ROMThe control unit can be built as a large ROM
Instruction
RESET
IRQ
PCSEL
SEXT
WASEL
WDSEL
ALUFN
Sub Bool Shift Math
WR
WERF
ASEL
BSEL
X 1 X 4 0 0 0 0 00 0 0 0 0 0 0X 0 1 6 0 3 0 0 00 0 0 0 0 0 0
add 0 0 0 0 0 1 0 00 0 1 0 1 0 0sll
andilwswbeq Problem Set #
6!
SummarySummary We have designed a full “miniMIPS” processor!We have designed a full “miniMIPS” processor!
has datapath, which includes registers, ALUhas datapath, which includes registers, ALU instruction and data memoriesinstruction and data memories control unit governs everything!control unit governs everything!
Next couple of classes: some advanced topicsNext couple of classes: some advanced topics memory hierarchy: caches etc.memory hierarchy: caches etc. pipelining the processor: benefits and challengespipelining the processor: benefits and challenges wrap up (grades etc.)wrap up (grades etc.)
Don’t forget: Problem Set #6 and Quiz #5Don’t forget: Problem Set #6 and Quiz #5
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