Connecting MATLAB & Simulink with your SystemVerilog ... · Connecting MATLAB & Simulink...

1© 2014 MathWorks, Inc.

Connecting MATLAB & Simulink with your

SystemVerilog Workflow for Functional

Verification

Corey Mathis

Industry Marketing Manager – Communications, Electronics, and Semiconductors

MathWorks

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Who is MathWorks?

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System Design & Simulation in Simulink

Model continuous-time and

discrete-time components

together

Express analog filters as

Laplace transforms or RLC

circuits

Variable step ODE solvers

Feedback control loops,

VCOs, PLLs

Unique advantages

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ASIC/SoC Design FlowModel-Based Design Integration

AS

IC/S

oC

-LE

VE

L T

ES

T &

VE

RIF

ICA

TIO

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ASIC/SoC-LEVEL INTEGRATION

ALGORITHM INTEGRATION

ALGORITHM IMPLEMENTATION

ALG

OR

ITH

M T

ES

T &

VE

RIF

ICA

TIO

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RF

AnalogHDL

TransistorMCU DSP FPGA ASIC

C/C++

MODEL GENERATION

ALGORITHM DESIGN

Environment Models

Timing and Control Logic

Digital Models RF ModelsAnalog Models

Algorithms

REQUIREMENTSRESEARCH

SystemC SystemVerilog

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Design GapHow to bridge MathWorks tools and EDA tools?

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How do I reuse AMS models from Simulink in an EDA environment?

How can I reuse my testbench for digital ASIC verfication?

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Co-simulation with Simulink

Verify the detailed level design:

– within the context of a full system simulation

– using the visualization and analysis capabilities of Simulink and

MATLAB

– testing each module independently of other modules

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Using Co-simulation for Model Elaboration

Ideal behavioral model

Cosimulation

Refined model

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SystemVerilog Testbench Environment

System Verilog DPI-C Component GenerationReuse of models in SystemVerilog Testbench

Develop– System components (IP and test

benches) in Simulink and MATLAB

– Model, Simulate, and Verify

Export– Components as C code with

SystemVerilog wrappers

Integrate– DPI-C components in Virtuoso and

Incisive

Verify– Verification of the complete system

design!

Algorithmic System-level Testbench

Component

ModelAnalysis

Component

Model

Environment

Model

Data

Source

Alg

ori

thm

Component

Model

DPI-C

Embedded Coder

HDL Verifier

DPI-C DPI-C DPI-C

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Using C Code Generation and the DPI-C Interface

1. Generate C code from your Simulink model

2. Automatically wrap the C code using the DPI-C interface

3. Import, build and simulate an equivalent behavioral

SystemVerilog model in your IC design tool

Simulink

3. Cadence

2. SystemVerilog wrapper

1. C Code

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Benefits of C Code Generation and DPI-C Export

Fast simulation using the native SystemVerilog API

IC design tool independent

Customizable approach supported by MathWorks

Leverages mature C code generation technology

Most suitable for testbench generation and IC verification

Support discrete and continuous time signals

Simulink

Cadence

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Some Details …

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Mixed-Signal ADC Model

Sine Wave

Signal Source

Analog

Low Pass Filter

First Order

Sigma Delta

Digital

Decimator Filter

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Export of Mixed-Signal Models

Continuous time signals

Discrete time solver

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From Variable to Fixed Time Step Solver

Chose a fixed sample time that it is small enough to

give correct results

Tradeoff accuracy and simulation time

Large time step Small time step

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Fast Rate

Clocks in SystemVerilog Determine the

Scheduling of the Execution

Simulink handles multi-rate systems automatically

Simulink supports model generation for hierarchical subsystems or individual

components

Need to define multi-rate clocks to schedule the SystemVerilog execution

when different rate components are generated

Slow Rate

Fast Clock Slow Clock

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Model Analog Circuits with Simscape

Model analog electronics with Simscape

Generate a SystemVerilog component for simulation in

the IC Design Tools

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Digital Workflow

HDL Coder

– Used to generate synthesible RTL

HDL for design models

SystemVerilog DPI-C

– Reuse of golden testbench: Signal sources

Enviorment and channel models

Measurement block and algorithms

Support for

– MATLAB

– Simulink

– Stateflow

SystemVerilog Testbench Environment

Algorithmic System-level Testbench

Component

ModelAnalysis

Component

Model

Environment

Model

Data

Source

Alg

ori

thm

Component

Model

DPI-C

HDL Coder

RTL HDL

(VHDL, Verilog)RTL HDL

(VHDL, Verilog)DPI-C

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Digital Workflow Example

MathWorks can export HDL code for pure digital models

Testbenches need to be exported to Cadence via DPI-C

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1. Generate synthesizable Verilog or VHDL for design components

Digital Workflow Example

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2. Generate C code with SystemVerilog wrappers for testbench components

Digital Workflow Example

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3. Import HDL and SystemVerilog into Cadence for simulation/verification

Digital Workflow Example

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Certified by STARC

http://www.mathworks.com/company/newsletters/articles/a-next-generation-workflow-for-system-level-design-of-mixed-signal-integrated-circuits.html

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MATLAB & Simulink provide a diverse environment for

early stage design exploration

Co-simulation provides a means of elaborating on initial

behavioral models to match detailed level designs

The DPI-C link for SystemVerilog provides a robust way of

exporting behavioral models from MathWorks tools into

Cadence for the purpose of functional verification

SystemVerilog Workflow Summary

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Q / A