Deep Trench Capacitors for Switched Capacitor Voltage...

IBM Research

Deep Trench Capacitors for Switched Capacitor Voltage Converters

Jae-sun Seo, Albert Young, Robert Montoye, Leland Chang

IBM T. J. Watson Research Center

3rd International Workshop for Power Supply on ChipNov 17th, 2012

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Outline

Motivation

Switched-capacitor voltage converter with deep trench capacitor technology

Design Tradeoffs for Efficiency and Current Density

Chip floorplanning / Application

Summary

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IBM Research

Chip~1V

R L>1V

C4

Power Delivery w/ 2:1 Step Down

Chip

~2V

R L2:1

~1V>2V

Today

ProposalReduce currentdelivery by 2x

I2R LossReduces by 4x C4 current

Reduces by 2xLdI/dtReduces by 2x

Net improvement: 4x(including conversion)

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Previous Work on On-Chip Voltage Conversion

Typically 3 approaches : (1) linear (2) switched-capacitor (3) buck –Linear regulator not suitable for high-voltage power delivery

Difficult to achieve high efficiency & current density simultaneously

>90% Efficiency

[1] Le, ISSCC10, 32nm[2] Ramadass, ISSCC10, 45nm[3] Kwong, ISSCC08, 65nm[4] Hazucha, JSSC05, 90nm[5] Wibben, JSSC08, 130nm[6] Abedinpour, ISSCC06, 180nm[7] Patounakis, JSSC04, 250nm[8] Kim, JSSC12, 130nm[9] Sturken, ISSCC12, 45nm

*Assumption: 1V, 200W, 500mm2

<10% μP Area*

1E-3 0.01 0.1 1 1050

60

70

80

90

100

hybrid [9][8]

[1]

[7]

[6]

[5]

[4]

[3]

On-chip C On-chip L On-package L

Effic

ienc

y [%

]

Output Per Converter Area [A/mm2]

[2]

Goal

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Why Switched-Capacitor Converters?High-voltage power delivery

Offers strong benefits especially for high-current applications or when significant package loss existsAchievable by switched-capacitor voltage converters with fixed ratio step-down Linear regulator : no high-voltage delivery benefit

Low-cost on-chip integration with existing technologyBuck converter : on-chip inductor material with high-enough Q not quite there, external inductors not good for integration

With dense deep trench capacitors, switched-capacitor converter can achieve high-efficiency and high current density

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IBM Research

Outline

Motivation

Switched-capacitor voltage converter with deep trench capacitor technology

Design Tradeoffs for Efficiency and Current Density

Chip floorplanning / Application

Summary

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IBM Research

2:1 Switched-Capacitor Converter

Vout = ½ Vin(1–Δ)

Iout = 2ΔCVinf

Intrinsic efficiency = (1–Δ)

Vin

Vout

Vin

Vout

Q=CΔVin

Vin

Vout

Q=CΔVinnon-overlapping clocks

φ

φ∗

VDD

VDD

0

0

φ∗

φ

φ∗

φ

φ∗

φ

φ∗

φ

φ∗

φ

φ∗

φ

Small Δ offset in Vout generates currentWith traditional capacitor, cannot really achieve intrinsic efficiency or sufficient output current

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High performance SOI CMOS– Yields low loss switch– Floating body FET with buried oxide isolation

• Facilitates stacking of thin-oxide devices for high voltage conversion

Deep trench capacitor– High density, low loss vs. MOS capacitor:

• Area efficiency: >25× better density• Conversion efficiency: >10× better parasitics

– High-κ storage node dielectric introduced in 32nm, metal liner mitigates poly depletion

Deep Trench Capacitor Technology

32nm SOI eDRAM(Wang, IEDM 2009)

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Scaling Trend of Deep Trench CapacitorIBM’s embedded DRAM implemented with deep trench capacitorSince 180nm, cell size reduced ~60% every node

eDRAM cell capacitance density scales well, path shown for 22nm

Wang, IEDM 2009

New technology elements + modest increase in trench AR → optimal storage capacitance

TiN inner electrode

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Multiple Conversion Ratios (3:1, 3:2, …)

Different conversion ratios, reconfigurable converters, hybrid conversion schemes are possible

However, they require more area (than 2:1), not necessarily favorable in terms of current density for high-current microprocessors

–Depends on whether the application requires a continuously wide range of output voltages

Ramadass, ISSSCC 2010 Le, ISSSCC 2010

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Outline

Motivation

Switched-capacitor voltage converter with deep trench capacitor technology

Design Tradeoffs for Efficiency and Current Density

Chip floorplanning / Application

Summary

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IBM Research

2:1 Switched-Capacitor Converter Circuits

Using level shifters / stacked buffers, no thick-oxide devices required

External supplies of negligible current for φ/φ* generation

Vhigh

VmidLevelShift

in

in

ConverterVhigh-to-VmidBuffers

Non-OverlappingClock Generation

Vmid-to-gndBuffers

Clock

φ∗φ

φ∗φ

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2:1 Switched-Cap Single-Phase Design Point

Vout = ½*Vin*(1-Δ)

Iout = 2*C*Vin*Δ*f

Efficiency = 1-Δ-k*W*f

Trade-off in efficiency, area, output current by selecting Vin, C, W, frequency, etc.

Objective: high efficiency with that satisfies required output current for an application

Vin

Vout

φ∗

φ

φ∗

φ

C

Wfrequency= f

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Efficiency / Output Current OptimizationFor a certain application, following specs will be fixed

– Target supply voltage– Required output current– Allowable area for SC

converters → fixed flying cap

Still, designers have freedom on the following to optimize efficiency

– Vin (Δ)– Switch sizes– Frequency

– Need to keep balance between Δ losses and switching (W, freq.) losses

Design point

Ioutrequirement

Vin

Vin

fixed C, Vout

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Measurements of 45nm 2:1 SC Converter

Output current is bounded by flying cap charge (when freq. is low), and RC of switch (when freq. is high)Achieved 90% efficiency (Δ~5%, clock losses ~5%) with 2.3A/mm2

– Higher current density achievable by trading off efficiency

Chang, VLSI Symp. 2010

0 2 4 6 8 10

60

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80

90

0.81.01.21.41.6

Effic

ienc

y [%

]

ILoad [A/mm2]

V out [

V]

Freq=100MHz

2-to-0.95V conversion90% efficiency

2.3A/mm2

0 100 20060

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90

100

0

2

4

6

Effic

ienc

y [%

]

Frequency [MHz]

Charging-TimeLimited

Freq/Cap-Limited

I Load

[A/m

m2 ]

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Tradeoff: Efficiency vs. SC AreaOnce the output current requirement is set, spending more area for SC converters (flying capacitors) increases power efficiency

But eventually saturates due to minimum switching loss and Δ-related loss

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Outline

Motivation

Switched-capacitor voltage converter with deep trench capacitor technology

Design Tradeoffs for Efficiency and Current Density

Chip floorplanning / Application

Summary

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IBM Research

Vdd_

SCou

t

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Interleaved Switched-Cap Converters

Reduce output rippleMain processor clock could be tapped and divided for multiple phases

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Chip FloorplanningOne switched-capacitor tile consists of multiple interleaved SC converters

Multiple switched-capacitor tiles could be placed across a processor

Each tile has its own SC control, enable, duty cycle– Output could be all tied

together– SC converters near hot spots

would be turned on more frequently than idle spots

tile tile

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2-D implementation:Allocate certain area for SC

2-D / 3-D Implementation Options

Implementation depends on system requirements, area availability

SCconverters

Processor

Interposer

Substrate

μC4

C4Interposer ChipTechnology w/DT

Processor ChipDT not necessary

3-D implementation:Interpose chip for voltage

conversion/regulation

Processor

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Fast Switched-Cap Strategy for Processors

Needs accurate reference voltageOverall closed-loop latency is critical for

noise reductionInput voltage noise largely handled

against load fluctuations

Open-loop operation

Closed-loop regulation

If SC is fully ON, Vdd varies linearly with load currentSC could be turned on with a certain duty

cycle depending on output load current

DT flying capacitors also act as decoupling caps for Vin and Vdd

Ramadass JSSC10, Kim JSSC12

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Another Application – Stacked I/OStacked I/O for low voltage signaling

I/O load

VDD

~Vdd/2

φ

φ∗

φ

φ∗

Driver

Voltage Converter

Sense Amplifier

I/O load

Out0In0

In0

VDD

In1

In1

Inputs swing 0 to VDD

I/O swings 0 to VDD/2

I/O swings VDD to VDD/2

Driver

Outputs swing 0 to VDD

Sense Amplifier

US Patent Application # US 2011/0298440

Out1

deep trench capacitor

C

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High-voltage power delivery is beneficial to reduce power distribution losses, which could be achieved with switched-capacitor down-conversion

Deep trench capacitors enable switched-capacitor converter to achieve high efficiency and high output current

Clear scaling path is shown for deep trench capacitors towards 22nm and beyond

Design tradeoff exists between efficiency, area, output current

DT-based switched-capacitor circuits offer solutions for highly-efficient voltage regulation modules for various applications

Summary

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Thank you!