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Design of Power Electronics Reliability:
A New, Interdisciplinary Approach
M.C. ShawSeptember 5, 2002
Physics DepartmentCalifornia Lutheran University
60 W. Olsen Rd, #3750Thousand Oaks, CA 91360
(805) 493-3296mcshaw@clunet.edu
Overview - MCS 2
Dr. Vivek Mehrotra, Design and Reliability Department, RSC
Prof. Elliott Brown, Electrical Engineering Department, UCLA
Dr. Jun He, Packaging and Interconnect Department, Intel
Mr. Bruce Beihoff, Manager, Solid State Power Assembly Laboratory, RA
Acknowledgements
Overview - MCS 3
Converts AC power (fixed frequency, voltage) to AC Power (variable frequency, current, and voltage)
Enables exact control of speed (RPM) and torque of motorsMotors become controlled electromechanical energy converters.
Variable Speed Drive
Variable Speed Drive & Motor Automation System
Performance Metrics:• Power Density• Cost• Reliability
AC Motor
Overview - MCS 4
Variable Speed Drive and Motor Applications
• Factory assembly lines• Heating, ventilation and air-conditioning• Refrigeration• Disc drives / digital storage• Electric / hybrid vehicles - commercial and
military• Rail transport• Elevators• Actuation of e.g., military aircraft controls,
ship controls• Practically anything that moves!
Overview - MCS 5
Variable Speed Motor Drive Block Diagram
Variable Speed Motor Drive
AC / DC Power
ConversionHeatsink
Torque / Speed Control Electronics
Motor /Load
Solid StatePower
Assembly
Electrical Power
Electrical Power
Controlled Mechanical Power Output
Electrical Power Input Source
Overview - MCS 6
The “Heart” of the Motor Drive:The Solid-State Power Assembly
Silicon Power Transistors
Ceramic Insulation
Wirebonded InterconnectionsSoldered
Interconnections
Gel
PlasticHousing
Power Terminals
Metal Baseplate
Heatsink
Schematic Cross Section of Typical Solid State Power Assembly
Overview - MCS 7
Thermal Management Goal: Decrease Power Density Between Device & Heatsink
Baseplate Power Density ~ 105 W/m2
Heatsink Power Density ~ 103 W/m2
Silicon Transistor PowerDensity = 106 W/m2
5 hp Motor Drive Example
Overview - MCS 8
Thin, Large Area Solder Joints Unique to Solid-State Power Assemblies
Devices
Internal top view of a 1200A, 3300V solid-state module(courtesy: Eupec GmbH+ Co.)
1 cm
Examples of Buried,
Continuous Solder Layers
Copper-CladCeramic
Substrates
Devices
Substrate
Not to scale
Solder
Copper Baseplate
Baseplate
Solder
Schematic Side View
Overview - MCS 9
Heatsink
. .
.Device, Tj
Solder Joint Cracking/Delamination Raises Package Thermal Resistance
. .
Device Substrate
Solder
HeatFatigue Crack / Delamination
No Heat Flowb/c Fatigue Crack
~
Pristine condition
Damaged condition
Solder
Substrate
Heat
After Some Period of Operation
Overview - MCS 10
Stress, σ (∼ ∆α∆Τ)σ (∼ ∆α∆Τ)σ (∼ ∆α∆Τ)σ (∼ ∆α∆Τ)
h Silicon Device
Substrate
Crack
Driving Force for Delamination: Mechanical Strain Energy Release Rate, GI
= GI( )E1hZ 22 υ−σ
Mechanical strain energy release rate, GI, is the “applied load”
Z ~ 0.3 for this geometryE = Young’s modulusν = Poisson’s ratioσ = In-plane mechanical stressh = Top layer thicknessGI = Applied strain energy release rate∆α = Coefficient of thermal expansion mismatch∆T = Range of temperature excursion
Solder Interface
Overview - MCS 11
Experimental Methodology: Materials and Architectures
Four solder compositions:97.5Pb/1.5Ag/1.0Sn (Tm=309°C)80Au/20Sn(Tm=280°C)96.5Sn/3.5Ag(Tm=221°C)63Sn/37Pb(Tm=183°C)
Silicon Chip
1/4” Copper Substrate
HhcSolder, hs
Z
X
Y
Stress, σ + σ σ + σ σ + σ σ + σ xx yy
Three silicon device sizes:Small: 0.2” squareMedium: 0.6” squareLarge: 1.0” square
Three substrate coefficients of thermal expansion (CTE)Low: Kovar (~ 6 ppm/°C)Medium: mild steel (~12 ppm/°C)High: copper (~17 ppm/°C)
1 inch
Test Article
Overview - MCS 12
Different Solders Exhibit Large Differences in Delamination
80Au-20SnSolder
63Sn-37PbSolder
As Soldered 1 cycle 10 cycles 100 cycles 1000 cycles
∆α∆α∆α∆α = 14.1 ppm /ºC
Cu
Si
Sn-Pb or Au-Sn Solder
∆α∆α∆α∆α = 14.1 ppm /ºC
0.6”
Ultrasonic Acoustic Micrographs
Intact Damaged
Intact Damaged
Overview - MCS 13
Stress, σ (∼ ∆α∆Τ)σ (∼ ∆α∆Τ)σ (∼ ∆α∆Τ)σ (∼ ∆α∆Τ)
h Silicon Device
Substrate
Crack
Recall: Driving Force for Delamination, GI
= GI( )E1hZ 22 υ−σ
Greater Damage Suggests Higher Stress and Higher GI…..Right?
Z ~ 0.3 for this geometryE = Young’s modulusν = Poisson’s ratioσ = In-plane mechanical stressh = Top layer thicknessGI = Applied strain energy release rate∆α = Coefficient of thermal expansion mismatch∆T = Range of temperature excursion
Solder Interface
Overview - MCS 14
0
50
100
150
200
250
480 500 520 540 560
Inte
nsity
(cou
nts/
seco
und)
Wavenumber (cm -1)
Silicon LO Phonon
Double Premonochromator Stag
Third Stage
Mono 3
Mono 2
Mono 1
Additive Mode Adaptation
CCD
AMPPMT
SPECTRAL DISPLAY
SAMPLE
LASER BEAM
VIEWING SCREEN
MICROSCOPE OBJECTIVE
PHOTOMULTIPLIER AMPLIFIER
Piezospectroscopy: Stress Mapping through Raman Spectroscopy
CuSiSi
• Stress-Sensitive Raman Peaks • Raman Probe Optical Path
Overview - MCS 15
200
400
600
800
1000
1200
1400
0 4 8 12 16 20 24Com
pres
sive
Stre
sses
, σxx
+σyy
(MPa
)
Position(mm)
80Au20Sn
95Sn5Ag
97.5Pb1.5Ag1Sn
63Sn37Pb
Solder Damage Depends on both Stress and Material Resistance
Intact
Damaged
σσσσSilicon
Substrate
Four different solders
Overview - MCS 16
Material Resistance, GIc, Depends on Degree of Cyclic Plastic Work, Wp
σ
Strain, εεεε
Stress, σσσσ
A.
B.
Strain, εεεε
Stress, σσσσ
A.
1) Plastic Work, Wp = ∫∫∫∫ σσσσ dεεεεp
2) Low-Cycle Fatigue Life, Nf ~ (Wp)m
~
Plastic Work, Wp
B.
C.
ε
Force, F
Plastic Response Elastic Response( Wp ~ 0 )
Overview - MCS 17
Stress, σσσσ
h Silicon Device
Substrate
Fatigue Crack
Delamination Only Occurs of GI is Greater than GIc
= GI vs. GIc( )E1hZ 22 υ−σ
Z ~ 0.3 for this geometryE = Young’s modulusν = Poisson’s ratioσ = In-plane mechanical stressh = Top layer thicknessGIc = Critical GI for fracture
Solder Interface, GIc
GIc is Intrinsic Material Property - GI is Applied Load
Overview - MCS 18
Thus, Fatigue Life Depends on Response of Solder Material as Compared to GI
Strain, εεεε
Stress, σσσσ
A.
B.
Strain, εεεε
Stress, σσσσ
A.
~
Plastic Work, Wp
B.
C.
Plastic Response:Low Stress (Low GI),
BUT ( Wp >> 0 ),so Low GIc (Crack Resistance)
Elastic Response:High Stress ( High GI)
BUT ( Wp ~ 0 )so High Gic (Crack Resistance)
IntactDamaged
Different Physical Damage Mechanisms Operate in Different Solders!
Difference in Peak Stress
GI Exceeds GIc GI Is Less Than GIc
Overview - MCS 19
Back to Our Problem: Unpredictable Performance Changes!
(Evans and Evans, IEEE Trans. Comp. Pack., Mfg. Tech., Part A, v. 21 no. 3 pp. 459 - 468, 1998)
Forward Voltage, Vbe
Number of Power Cycles, N
Packaged Bipolar Power
Transistor
Large Electrical Deviations May Occur During Operation
Should Remain Constant!!
Now we can apply our detailed knowledge of thermomechanical stress and response of solder
Overview - MCS 20
Predicted Electronic Parameter Shift Correlates with Experimental Data
(a)
0
0.5
1
10 100 1000 10000
Number of Cycles
Vbe
(V)
(b)Nc Nc
t = 0.8 t = 0.5
Experimental (Evans and Evans, IEEE CPMT, 1998)
Predicted
Cha
nge
in b
ase-
emitt
er
volta
ge( δδ δδ
V be)
2N3773 bipolar junction transistor
Time, t
Junc
tion
Tem
p, T
j
1 Cycle
C
E
B
Bipolar Transistor
2N3773 npn bipolarIC = 1.5 AVCE = 100 VPD = 150 W
“The Problem”
“The Solution”
t = silicon thickness
Overview - MCS 21
Conclusions
• Power Electronics Packaging Demands Highly Interdisciplinary Analyses, Experiments & Knowledge
• New Methodology Developed to Quantitatively Assess Device/Circuit/System Interactions Resulting from Degradation
• Rigorous, Physics-Based Coupling of Electronics / Mechanics / Materials / Heat Transfer
• Interfaces are Crucial
• Expanding Approach to Explore Biomechanics, Biomaterials Applications and Interactions
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