Bipolar transistor

23/4/19 Physics of Semiconductor Devices 1

理学院量子智能信息处理实验室

Bipolar transistor



§3-1 Introduction



Bipolar Transistor

First bipolar transistor (BJT) was invented in 1948

The term bipolar came from the fact that both types of carriers, i.e., electron and hole play important roles in operation

Field Effect Transistor (FET) is unipolar, in which only one type of carrier is important



Bipolar Transistor

In VLSI era, BJTs starts to lose their show stage due to the emergence of MOSFETs, which possess advantage of simplicity in term of process and circuit design However, BJT’s refuse to step down because of their high current drive capability and superior analog performance (also useful in power applications) Current trend is to combine the best of MOSFETs and Bipolar devices, which is known as BiCMOS process BJT devices are also the preferred device for high speed (e.g. Emitter Couple Logic .ECL) and RF applications



Bipolar Transistor

n+

p n

p+

n p


理学院量子智能信息处理实验室Bipolar Transistor

The ”Planar Process” developed by Fairchild in the late 50s shaped the basic structure of the BJT, even up to the present day.



Modern BJT





Close enough that minority carriers interact (negligible recombination in base)

BJT basically consists of two neighbouring pn junctions back to back:

For apart enough that depletion regions don’t interact (no “punchthrough”)

Uniqueness of BJT: high current drivability per input capacitance fast excellent for analog and front-end communications applications.



Bipolar operation

Operation depends on the bias condition

IB

IC

IE



§3-2 Carrier distribution


理学院量子智能信息处理实验室Current Flow

emitter current injected into the base

base current injected into the emitter

recombination in the base current region

reverse biased current across the BCJ

reverse biased current across the BCJ

electron current from the emitter

EBnI

BEpI

BERI

CBpI

CBnI

CnI



Bipolar TransistorModes of

operation

VCB

SaturationForward active

CutoffInverted active

VEBPNP NPN

SaturationForward active

CutoffInverted active

VBC

VBE

activeinvertedsaturationcutoff

forwardreverseforwardreverse

forward

reverse

reverse

forward

E-B C-B Mode



An idealized p-n-p transistor in thermal equilibrium, that is ,where all there leads are connected together or all are ground.

The impurity densities in the three doped regions, where the emitter is more heavily doped than the collector. However the base doping is less than the emitter doping, but greater than the collector doping.



Transistor Action

ACTIVE MODE

In active mode, the emitter-base junction is forward biased and collector base-junction is reverse biased.


理学院量子智能信息处理实验室Current FlowForward bias Reverse bias

Electron FlowHole Flow



Transistor Action

Saturation Mode

Both junction are in forward bias

Cutoff Mode

Both junctions are in reverse bias and all currents in the transistor are zero.

Inverse-active Mode

Junction between E and B is in forward bias and junction between B and C is in reverse bias.



Current Gain

IE=IEp+IEn

IC=ICp+ICn

IB=IE-IC=IEn+(IEp-ICp)-ICn



Current GainCommon base current

gain

Emitter efficiency

Base transport fact

Ep

Cp

EnEp

Ep

EnEp

Cp

E

Cp

I

I

II

I

II

I

I

I00

EnEp

Ep

E

Ep

II

I

I

I

Ep

CpT I

I

T 0



Collector current

CB: current measured between these two terminals

O: refers to the state of the third terminal with respect to the second

CBOEC III 0



Carrier Profile in Active Mode



Carrier distribution in this region

To derive the current-voltage expression for an ideal transistor, we assume the following:

1. The device has uniform doping in each region.

2. The hole drift current in the base region as well as the collector saturation current is negligible.3. There is low-level injection.

4. There are no generation-combination currents in the depletion region.

5. There are no series resistance in the devices.



Carrier Distribution in each RegionBase

regionSteady-state continuity equation

The general solution is

002

2

p

nnnp

pp

dx

pdD

pp LxLxnn eCeCpxp 21

Where is the diffusion length of holes.

ppp DL

where and are the diffusion constant and the life time of minority carriers, respectively.

pD p



By the boundary conditions for the active mode:

the solution can expressed

When W/Lp<<1, the distribution equation can be simplified as

kTqVnn

EBepp 00

0Wpn

0Wpn

p

p

n

p

pkTqVnn

L

W

L

x

p

L

W

L

xW

epxp EB

sinh

sinh

1

sinh

sinh

1 00

W

xp

W

xepxp n

kTqVnn

EB 1010



Carrier distribution



Carrier Distribution in each RegionEmitter and collector region

The boundary condition in the neutral region and collector region are:

When nE0 and nC0 are the equilibrium electron concentrations in the emitter and collector, respectively. Substituting these boundary conditions into expressions similar to Eq.1 yields

kTqV

EEE

EBenxxn0

00

CBVq

CCCenxxn

E

E

EB L

xx

kTqV

EEEeennxn

100

C

C

L

xx

CCCennxn

00

Exx

Cxx



Common base Active mode is BEJ forward biased while

CBJ reverse biased Saturation occurs when CBJ is forward biased When IE=0, the device is cutoff, IC is the reverse leakage current of the CBJ. Note that IC≠0 for VCB=0. The current is contributed by IE if the BEJ is forward biased.



Common base configuration

Minority carrier distributions in the base region of a p-n-p transistor.

a) Active mode for VBC=0.

b) Saturation mode with both junctions forward biased.



Common emitter

Saturation occurs when both EBJ and CBJ are forward biased Active mode is the most useful for linear applications Saturation and cut-off modes are most useful for switching applications



Common emitter configuration

Common emitter current gain

00 CBCBC IIII

0

0

0

0

11

CB

BC

III

0

00 1 CB

CE

II

00 CEBC III

0

00 1

B

C

I

I



§3-3 Current-voltage characteristics of ideal BJT



Ideal BJT



Ideal BJT simplifications:

1D Uniform doping distributions. Minority carrier G&R in intrinsic base is negligible. Emitter extrinsic base and collector also assumed “short” from minority carrier point of view. Low level injection. QNR thicknesses independent of VBE and VBC. Ignore sidewall effects. No parasitic resistances. Ignore substrate.



Simplified 1D model of intrinsic device:



Regimes of operation:



Basic operation in forward regime:Two junctions back-to-back:



VBE>0Injection of electrons from E to B

Injection of holes from B to E

VBC<0

Extraction of electrons from B to C

Extraction of holes from C to B

IB -IE>>IC



Transistor effect: electrons injected from E to B, extracted by C



In forward-active regime:

VBE controls IC (“transistor effect”)

IC independent of VBC (“isolation”)

Price to pay for control: IB



Carrier profiles in TE and FAR:





Dominant current paths in forward active regime:



IC: electron injection from E to B and collection into C IB: hole injection from B to E

IE=-IC-IBKey dependencies (choose one):IC on VBE: , ,none,

other

IC on VBC: , ,

IB on VBE: , ,

IB on VBC: , ,

IC on IB: exponential, quadratic, none, other

none, other

none, other

none, other

kTqVBEe

kTqVBEe

kTqVBCe

kTqVBCe

BEV1

BEV1

BCV1

BCV1



Forward-active regime (VBE>0,VBC<0)



Boundary conditions:

Electron profile:

Electron current density:

0,exp0 0 BBBE

BB WnkT

qVnn

BBB W

xnxn 10

B

BB

BBeB W

nqD

dx

dnqDJ

0



Collector current scales with area of base-emitter junction AE:



Collector terminal current :

or

kT

qV

WN

DnqAAJI BE

BB

BiEEeBC exp

2

kT

qVII BE

SC exp

Collector saturation currentSI



Base current: focus on hole injection and recombination in emitter (assume “short” or “transparent” and S= at surface)



Boundary conditions:

Hole profile:

Hole current density:

00 ,exp EBEEEBE

EBEE pxWpkT

qVpxp

00 1 EE

BEEBEEE p

W

xxpxpxp

E

EBEEE

EEhE W

pxpqD

dx

dpqDJ 0



Base current scales with area of base-emitter junction AE:

Base terminal current:

1exp1exp

2

kT

qVI

kT

qV

W

D

N

nqAAJI BE

F

SBE

E

E

E

iEEhEB



Gummel plot:





Key conclusions

BJT is minority-carrier type device: in npn BJT in forward active regime: Emitter “injects” electrons into Base, Collector “collects” electrons from Base.

IC controlled by VBE, but independent of VBC (transistor effect):

Base injects hole into emitter IB depends only on VBE

kT

qVII BE

SC exp

1exp

kT

qVII BE

F

SB



Key questions:

How does the BJT operate in other regime?

How does a complete model for the ideal BJT look like?



Forward-active regime (VBE>0, VBC<0)



1exp

kT

qVII BE

F

SB

1expexp

kT

qVI

kT

qVIIII BE

F

SBESBCE



Current gain

BEB

EBE

E

E

E

i

B

B

B

i

B

CF WDN

WDN

W

D

N

n

W

D

N

n

I

I

2

2


理学院量子智能信息处理实验室F

To maximize :F

NE>>NB

WE>>WB (for manufacturing reasons, WE≈WB) want npn rather than pnp, because this way DB>DE

hard to control if is high enough (>50), circuit techniques effectively compensate for this.

FF





Equivalent circuit model



Energy band diagram



Summery of minority carrier profiles (not to scale)



Reverse regime (VBE<0,VBC>0)IE: electron injection from C to B, collection into E

IB: hole injection from B to C, recombination in C



Minority carrier profiles (not to scale):



Current equations (just like FAR, but role of collector and emitter reversed):

kT

qVII BC

SE exp

1exp

kT

qVII BC

R

SB

1expexp

kT

qVI

kT

qVIIII BC

R

SBCSBEC



Equivalent-circuit model representation:



Prefactor in IE expression is IS: emitter current scales with AE.



But, IB scales roughly as AC:

downward component scales as AC

upward component scales as AC-AE ≈AC

Hence, <<

51.0 R F



Energy band diagram:



Cut-off regime (VBE<0,VBC>0)

IE: hole generation in E, extraction into B.

IC: hole generation in C, extraction into B






Current equations:

F

SE

II

R

S

F

SB

III

R

SC

II

These are tiny leakage currents (~10-

12A)



Equivalent circuit model representation:



Energy band diagram



Saturation regime (VBE>0,VBC>0)IC,IE: balance of electron injection from E/C into B

IB: hole injection into E/C, recombination in E/C, respectively






Current equations: superposition of forward active + reverse:

1expexpexp

kT

qVI

kT

qV

kT

qVII BC

R

SBCBESC

1exp1exp

kT

qVI

kT

qVII BC

R

SBE

F

SB

kT

qV

kT

qVI

kT

qVII BCBE

SBE

F

SE expexp1exp

IC and IE can have either sign, depending on relative magnitude of VBE and VBC and F R



Equivalent circuit model representation (Non-linear Hybrid- Model):

Complete model has only three parameters: IS, and .

F R



Energy band diagram:



In saturation, collector and base flooded with excess minority carriers take lots of time to get transistor out of saturation.



Key conclusions

In FAR, current gain maximized if NE>>NB.

F

hard to control precisely: if big enough (>50), circuit techniques can compensate for variations in .

F

F

BJT design optimized for operation in forward-active regime operation in inverse is poor: << .

RF

In saturation, BJT flooded with minority carrier takes time to get BJT out of saturation.



Hybrid- model: equivalent circuit description of BJT in all regimes:

Only three parameters needed to describe behavior of BJT in four regimes: IS, and .F R



Key questions

How do the output characteristics of the ideal BJT look like?

How do the charge-voltage characteristics of the ideal BJT look like?

What is the topology of the small-signal equivalent circuit model of the ideal BJT in the FAR? What are the key dependencies of its elements?



Ideal BJT current equations (superposition of forward active + reverse)

1expexpexp

kT

qVI

kT

qV

kT

qVII BC

R

SBCBESC

1exp1exp

kT

qVI

kT

qVII BC

R

SBE

F

SB

kT

qV

kT

qVI

kT

qVII BCBE

SBE

F

SE expexp1exp



Equivalent circuit model representation:

Complete model has only three parameters: IS, and .

F R



Common-emitter output I-V characteristics









I-V for Active Mode

kTqVnp

xx

nPEp

EBeW

pqAD

d

dpqDAI 0

0

kTqVnp

Wx

npCp

EBeW

pqAD

dx

dpqDAI 0

10

kTqVEE

xx

EEEn

EB

E

eW

nqAD

dx

dnqDAI

C

CC

xx

CCCn L

nqAD

dx

dnqDAI

C

0

IE=IEp+IEn

IC=ICp+ICn

W/Lp<<1



1211 1 aeaI kTqVE

EB

0

0011

E

EEnP

L

nD

W

pDqAa

W

pqADa np 012

2221 1 aeaI kTqVC

EB

W

pqADa np 021

C

CCnp

L

nD

W

pDqAa 00

22



E

B

B

E

E

B

x

x

D

D

N

NB

1

1

Emitter efficiency

(xB<<LB), (xE<<LE)

How to improve emitter efficiencyWe should decrease the ratio of NB/NE



General I-V for various modes

Base of EBERS-MOLL Model

11 1211 kTqVkTqVE

CBEB eaeaI

11 2221 kTqVkTqVC

CBEB eaeaI



I-V for active mode

1211 1 aeaI kTqVE

EB

0

0011

E

EEnP

L

nD

W

pDqAa

W

pqADa np 012

2221 1 aeaI kTqVC

EB

W

pqADa np 021

C

CCnp

L

nD

W

pDqAa 00

22




RRFE III RFFC III

10 kTqVFF

EBeII

B

B

EE

EiF WN

D

NL

DqAnI 2

0

10 kTqVRR

CBeII

CC

C

B

BiR NL

D

WN

DqAnI 2

0




RRFE III RFFC III

RRFFCEB IIIII 11

B

BiRRFFS WN

DqAnIII

2

00

F

FF

1

R

RR

1



§3-4 Charge-voltage characteristics of ideal BJT



In BJT, two types of stored charge:

depletion layer charge

minority carrier charge

In forward-active regime:



Depletion layer charge

In B-E and B-C SCR’s respectively

BE

BEbiEBEEjE NN

VNqNAQ

2

CB

BCbiCCBCjC NN

VNqNAQ

2

are respective built-in potentials.

biE biC



Since NE>>NB>>NC

Depletion capacitance:

BEbiEBEjE VqNAQ 2

BCbiCCCjC VqNAQ 2

biE

BE

je

BEbiE

BE

BE

jEje

V

C

V

qNA

V

QC

12

0

biC

BC

jc

BCbiC

CC

BC

jCjc

V

C

V

qNA

V

QC

12

0



Minority carrier charge

Key result from pn diode: in “short” or “transparent” QNR:

Stored charge=minority carrier transit time × injected minority carrier current

Diffusion capacitance.

Excess minority carrier in QNR’s excess majority carriers to keep quasi-neutrality



For emitter in FAR:

with hole transit time

BtEE IQ

E

EtE D

W

2

2



For base in FAR:

with electron transit time:

CtBB IQ

B

BtB D

W

2

2



Comments:

Units of QB and QE are C.

QE and QB scale with AE.

Total minority carrier in FAR:

CFCtBF

tECtBBtBBEF IIIIQQQ



F intrinsic delay [s]

tBF

tEF

is overall time constant for minority carrier storage in BJT in FAR:

F



Note: emitter contribution to is because IB is times smaller than IC.

FF

FtE

If VBE changes, QE and QB change capacitive effect:

kT

qI

dV

dQC C

FBE

FF



Location of this capacitance? Think of which terminals supply stored change (minority and majority carriers):

For QE:

minority carriers (holes) injected from base

majority carriers (electrons) come from emitter contactFor QB:

minority carriers (electrons) injected from emitter majority carriers (holes) come from base contact



Equivalent-circuit model:



Similar picture in reverse regime: charge storage in base and collector

a bit complicated because it accounts for charge storage in intrinsic and extrinsic base and collector regions.

RERR IQ



Diffusion capacitance:

Located between base and collector terminals.

kT

qI

dV

dQC E

RBC

RR



By superposition, complete equivalent circuit model valid in all four regimes:



§3-5 Small-signal behavior of ideal BJT



In analog (and digital) application, interest in behavior of BJT to small-signal applied on top biasSmall signal equivalent circuit

model.



Small-signal equivalent circuit model in FARMust linearize hybrid- model in FAR:



-Non-linear voltage-controlled current source linear voltage-controlled current source.

-Diode linearized to resistor.

-Charge storage elements linearized to capacitance.



Linearized voltage-controlled current sourceApply small signal vbe on top of bias

VBE.



kT

qvI

kT

qv

kT

qVI

kT

vVqIiI be

CbeBE

SbeBE

SCC 11expexp

Small signal collector current:

Define transconductance:

gm depends only on absolute value of IC and T (unlike MOSFET, where gm depends on device geometry)

Collector current:

beC

C vkT

qIi

kT

qIg C

m



Linearized diode



kT

qv

kT

qVI

kT

vVqIiI beBE

F

SbeBESbB 1expexp

Base current:

Small-signal base current:

beB

b vkT

qIi

Define conductance:

Then, in general,

F

m

F

CB gI

kT

q

kT

qIg

mgg



capacitors

QjE Cje

QjC Cjc

QF C



Two components in C :

Note:

mF gC



Small-signal equivalent circuit model for ideal BJR in FAR:



Key conclusions

Emitter contribution to is times smaller than because IB is times smaller than IC

F F

FtE

tBF

tEF

In BJT, two types of stored charge: depletion layer charge and minority charge.

Depletion layer charge accounted through depletion capacitances.

Minority carrier charge accounted through time constant (intrinsic delay):F



Non-linear hybrid- model for ideal BJT including charge storage elements:



Small-signal equivalent circuit model of ideal BJT in FAR:

with:

kT

qIg C

m F

mB g

kT

qIg

mF gC



§3-6 Frequency Characteristics



Common-emitter short-circuit current-gain cut-off frequency, fT



fT: high-frequency figure of merit for transistors

Short-circuit means from the small-signal point of view.

BJT is biased in FAR.





Focus on small-signal current gain:

Definition of fT: frequency at which |h21|=1.

For low frequency, h21 , for high frequency h21 rolls off due to capacitors.

F

021

cevb

c

i

ih



Small-signal equivalent circuit model:



Then:

Magnitude of h21:

bejcbemc vCjvgi

bejcjeb vCCCjgi

jcje

jcm

CCCjg

Cjgh

21

222

222

21

jcje

jcm

CCCg

Cgh



222

222

21

jcje

jcm

CCCg

Cgh

Bode plot of |h21|:



Three regimes in |h21|:

jcje

jc

CCC

Ch

21

jcje

m

CCC

gh

21

Fm

g

gh

21

intermediate frequency,

low frequency,

c

high frequency,

c



Angular frequencies that separate three regimes:

Angular frequency at which |h21|=1:

jcje CCC

g

jc

mc C

g

jcje

mT CCC

g



In terms of frequency:

Note:

jcje

mT CCC

gf

2

F

T



Physical meaning of fT

fT has units of time. Define delay time:

21

Four delay components in .

d

m

jc

m

je

F

tEtB

m

jc

m

je

mTd g

C

g

C

g

C

g

C

g

C

f

2

1



Consider response of BJT to a step-input base current:



bBB iII

beBEBE vVV

bFCcCC iIiII

At 0t

As t



How much time does it takes for ic to reach its final value?



Charge must be delivered to four regions in BJT: Quasi-neutral emitter

Quasi-neutral base

Emitter-base depletion region

Base-collector depletion region

btEe iq

ctBb iq

cm

jebejeje i

g

CvCq

cm

jcbejcbcjcjc i

g

CvCvCq



Charge delivered at constant rate to base. Time that it takes for all charge to be delivered:

fg

C

g

C

i

qqqq

m

jc

m

jetBFtE

b

jcjebe

2

1



How much time does it take for ic to build up to IC + ib ?

: delay time before ic increase to

bFC iI

f2

1

: delay time before ic increase to bC iI T

d f

2

1

Since ,

bFc ii

Tm

jc

m

jetB

F

tE

Fd fg

C

g

C

2

1



With sinusoidal input:

fraction of that goes into capacitance

cbe ivbif

bc ii At fT:



Key dependencies of fT in ideal BJTfT dependence on IC:

Rewrite fT:

C

jcje

F

Fjcje

mT

I

CC

q

kTCCC

gf

1

1

2

1

2



Two limits:

Small IC: limited by depletion capacitances

Large IC: limited by intrinsic delay (dominated by )

tB

FTf 2

1

jcje

CT CC

I

kT

qf

2





Alternative view of IC dependence:

Tm

jc

m

jetB

F

tEd fg

C

g

C

2

1



Standard experimental technique to extract and :jcje CC

F



fT dependence on VBC:

[but only in low IC regime of fT]

(B-C junction is more reverse biased)

CBV Tjc fC



Key conclusions fT: high frequency figure of merit for

transistors: frequency at which |h21|=1.

fT of ideal BJT:

jcje

mT CCC

gf

2

Delay time, :time it takes for step increase in iB to yield an identical step increase in iC.

Td f

2

1



Key questions

How can the frequency response of a BJT be engineered?

Why are the output characteristics of a BJT in FAR not perfectly flat?

What is the maximum voltage that the collector of a BJT can sustain in FAR? What are the key design issues for the break-down voltage?



Key dependencies of fT in ideal BJT (cont.)fT dependence on device

layout: For low IC: fT dominated by Cje, Cjc

If AE or AC (keep IC constant) Tf

C

jeE

m

je

I

CA

g

C 0

C

jcC

m

jc

I

CA

g

C 0

For high IC: fT dominated by intrinsic delay ;fT independent of AE or AC

F



Device design strategies for improving fT

Four delay terms in fT:

Strategies to reduce each delay component:

building steep doping profile in emitter.

Emitter charging time, , minimized by F

tE

small contribution to , not much payoff.

F

tE

d

having a shallow emitter ( ~ ),

tE 2EW

enhancing ,

F

m

jc

m

jetB

F

tE

Td g

C

g

C

f

2

1



introducing drift field in base (through impurity gradient or SiGe composition gradient).

reducing WB

( ~ ),tB 2

BW

Base transit time, ,minimized by

tB



Example 1 [Kasper 1993]

Significant device engineering towards minimizing .

tB



Example 2 [Yamazaki, IEDM 1990, p. 309]:





Example 3 [Crabbe, IEDM 1990, p. 17]:

Collector current dependence of fT at 298K and 85K for Si and SiGe devices. In both cases, the peak fT increase at lower temperature as well as the associated collector current.



E-B SCR charging time, Cje/gm:

Minimized by:

tailoring doping profiles at E-B junction

NB

C

je

C

jeE

m

je

J

C

I

CA

g

C 00



B-C SCR charging time, Cjc/gm:

Minimized by:

C

jc

E

C

C

jcC

m

jc

J

C

A

A

I

CA

g

C 00

NC

tailoring doping profiles at B-C junction. tightening layout of transistor: 1

E

C

A

A



2/1])(8

[eTbc

Tm LfrC

ff

)(8 22

eTbc

Tpm LfrC

ffG



§3-7 Non-ideal effects in BJT



Early effect: impact of VBC on WB

Reverse early effect: impact of VBE on WB

IB unchanged

, CBBCBC IWxV

smaller IC than ideal , BBEBE WxV

IB unchanged

F



Early effect: impact of VBC on WB

BCC VfI

Note: 0BC

B

dV

dW

VBC more negative BCCBCB VIVW



To capture first-order impact, linearize WB (VBC):

VA is Early voltage:

A

BCBCBBCB V

VVWVW 10

0

0

jc

BBA C

WqNV



Impact on IC:

kT

qV

VW

D

N

nqAVI BE

BCB

B

B

iEBCC exp

2

kT

qV

V

VVW

D

N

nqA BE

A

BCBCB

B

B

iE exp

10

2

A

BC

BCC

V

VVI

1

0

A

BCBCC V

VVI 10

since typically .BCA VV

Notice: .Then

0BCV CBC IV



Also, since IB unchanged:

A

BCBCF

A

BC

BCFBCF V

VV

V

VV

V 101

0



Manifestation of Early effect in output characteristics:



Main consequence of Early effect: finite slope in output characteristics in FAR: out put conductance.

With go given by:

A

C

V

Ig 0



Base-width modulationVBE and VBC affect xBC , respectively ).,( BCBEB VVfW



Kirk effect



s

CqN

dx

d

)( BCbi VVEdx



基区纵向扩展时的势垒区



基区有横向扩展时少子的运动情况



High Injection Effect(Webster Effect)



High Injection Effect

As VBE increases, the injected minority carrier concentration may approach, or even become large than, the majority carrier concentration.



High Injection Effect

Reduction in emitter injection efficiency, since JPE increases

Collector current will become an exponential function of VBE in terms of qVBE/2kT



dx

dnqDnEqJ nnn

dx

dPqDPEqJ ppp

dx

dPDPE pp

dx

dP

Pq

kTE

1

)()()( xnxNxP bB

)11

()(1

dx

dn

nNdx

dN

NnN

N

q

kTnN

dx

d

nNq

kTE b

bB

B

BbB

BbB

bB





High Collector Current Effect



High collector current effects

Then, as IC approaches:

satCECK NqAI

As IC↑, electron velocity in collector↑.

satBut,there is a limit:



The electrostatics of the collector are profoundly modifiedtransistor performance degrades:

To first order:

CKCpkC III 2



Key design issue: NC

F

Main origin: formation of current-induced base inside collector SCR effective quasi-neutral base width new delay

component

F Tpkf

TpkCKC fIN



Current Crowding Effect



Current Crowding



Current Crowding



Breakdown Effect



Avalanche breakdownSudden rise in IC for large reverse VCB.Key issue: breakdown voltage depends on terminal configuration:



Experimental observation:

BVCB0 < BVCB0



Common-base configuration: breakdown as in isolated p-n junction

Breakdown when M



Common-emitter configuration: BE and BC junctions interact in a positive feedback loop

Breakdown occurs at finite M and enhanced by high .

F

With IB=0 (or fixed), holes generated in B-C junction must be injected into E B-E goes into forward bias . CI



Key dependencise: CBOCEOC BVBVN ,



more than necessary!

CEOF BV but BVCBO unchanged don’t wantF

[Yamaguchi 1993]

Collector-to-emitter breakdown voltage dependent on current gain


理学院量子智能信息处理实验室Breakdown VoltageIn the extreme, the entire neutral region may be

totally depletedBand diagram illustrating punch-through

EB barrier lowered by VCE

When punch-through happens, there is no flat-band region in base( no quasi-neutral)

potential barrier seen by hole before punch-through

C

BCB

S

Bpt N

NNNqWV

)(

2

2



Avalanche Breakdown



§3-8 Switching Transistor









§3-9 Design of BJT















Junction-isolated BJT

First integrated BJT



Poly-Si emitter BJT



Problem of metal-contacted emitter: emitter thickness scales badly.

FBE IW

Poly-Si extension effectively increases emitter thickness:

Fpreserved when WE scales down.



Single-poly self-aligned BJT

Unique feature:- extrinsic base self-aligned to intrinsic device Bext

E

C RA

A,



Double-poly self-aligned BJT

Unique feature:- base contacts made on poly Si over isolation , smaller footprint

E

C

A

A



Selectively-implanted collector (SIC) BJT

Unique feature:- intrinsic collector doping level raised through self-aligned implant TC fJ ,max



Trench-isolated BJT

Unique feature:- deep-trench isolation SA



SOI-BJT

Unique feature:- silicon-on-insulator substrate , smaller footprint

SC



Epitaxial SiGe HBT

Unique features:- epitaxial base: enhanced thickness and doping control BTBB RfNW ,- Ge in base: heterojunction effect, drift field in base (if gradient in Ge composition) ABTS VRfI ,,,



Bipolar issues in CMOS



Latch up: interaction of two hidden BJT’s inside a CMOS pair.



In principle, no problem because in both BJTs, VBE=0.



But there are also two parasitic resistors:



More complete equivalent circuit model:

POSITIVE FEEDBACK LOOP can cause device destruction.

Suppose for some reason, current flows through RX pnp goes into FAR IC (pnp) ohmic drop in RW npn goes into FAR IC (npn) more ohmic drop in RX



Latch-up started by: Minority carrier injection into substrate by transient forward bias on pn junctions (typically in input or output circuits)

photogeneration by ionizing radiation impact ionization by hot carriers



Elimination of latch up:

Then do: use heavily doped substrate (need lower doping epi layer on top for devices) sufficient transistor spacing guard rings at sensitive locations

reduce RX and RW

reduce andnpn pnp



An advanced twin-well process for VLSI CMOS applications.The high-conductivity substrate reduces susceptibilty to

latch-up;the separately doped well regions provide precise control of MOSFET

characteristics.Adapted from R. S. Muller and T. L. Kamins.Device Electronics for integrated Circuits, 2nd ed, Wiley. 1986. p.

463.





the higher the trigger current, the higher the immunity to latch-up

larger n+ -p+ spacing better immunity

thinner epi on top of n+ -substrate better immunity



Guard ring: reverse-biased pn junction that collects injected holes.



Other bipolar effects in MOSFETs: Can’t implement floating pn diodes in CMOS process Breakdown and snap-back (bipolar-induced breakdown) Floating-body effects in SOI MOSFETs



Key conclusions

Bipolar effects pervasive in any device with multiple n and p regions.

CMOS latch-up interaction of parasitic npn and pnp BJTs; can lead to device destruction.

Maximum current: satCECpk NqAI

At high collector current, velocity saturation of electrons in collector performance degrades:

F Tf,

Megatrends of BJT development:footprint , vertical dimensions , JC , , ,BV

. f

Documents

Bipolar transistor