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Electronics Modification:Critical Design Delta Review 2
Tom Montagliano
July 27th, 2012
1
Open Items
Modifications
1.Perform noise measurement on larger scale2.Zoom into noise data and analyze3.Determine how current will be measured with Virgo attached4.Re-select protection diode that will not allow voltages over 5.7 V5.Gather more information on temperature sensor and develop action plan6.Re-simulate crosstalk with proper values for the input voltage7.Propose PCB layout, schematic and mounting
2
Noise analysis with varied time scales
Critical Design Delta Review 2
3
Noise analysis with different time scales on plot
4
x-axis=ADU y-axis = time (ms)
measurements made with current source addedCDS noise = 9.84 µV
measurements made with no current sourceCDS noise = 8.88 µV
Diode Selection
Critical Design Delta Review 2
5
Diode selection
1. The Vishay 5.65 V zener diode (TZX5V6D) is an ideal choice for our application since there is little current draw at 5V and the voltage drop will not exceed 5.7 V.
2. The Fairchild 5.6 V zener diode (1N5343BTR) is not as good as the Vishay diode for our application since there is relatively more current draw at 5V.
3. With 5 V on the bias line, the voltage across the diode will be 4.95 V for the Vishay diode and 4.87 V for the Fairchild diode.
4. CONCLUSION: The Vishay 5.65 V zener diode (TZX5V6D) will be used as the protection diode.
6
Temperature Sensor
Critical Design Delta Review 2
7
Temperature Sensor
1. There is 1 DT470-SD-12A located on the motherboard of the Virgo package.
2. This will be routed to the Lakeshore through the cabling and will not involve the electronics system.
8
DT470-SD-12A
Crosstalk Simulations
Critical Design Delta Review 2
9
Notes on Source-follower Transimpedance
1. It was suggested to assume RDS(on) = 2 kΩ, BUT:2. Using this value results in bogus simulation results (flat lines)3. PSPICE parameter “RDS”:
a. Description: “Drain-source shunt resistance”b. Units: ohms; Default value: infinity
4. We know that an ideal MOSFET acting as a switch will have RDS = 0 Ω5. Recall small-signal model of PMOS FET:
a. Ideally ro = infinity; so in PSPICE, RDS must be the same as ro.
b. The source/drain impedance when FET is “on” is a combination of gm, VGS, and ro. We don’t know this information without physical testing, or information from Raytheon.
1. For these simulations, we’re using an ideal PMOS FET
http://www.prenhall.com/howe3/microelectronics/pdf_folder/lectures/mwf/lecture12.fm5.pdf
Measured Rout of Leach +16.5 V
0
V s
1 6 . 5R L
R o u t
0
VL
RL (Ω) VL (V) IL (mA) Rout (Ω)
Inf. 16.585 0.0 n/a
1737.4 16.582 9.5441 0.314
259.16 16.5755 63.9586 0.1485
147.5 16.572 112.3525 0.1157
1. Measure VL with no load (VOC)2. Measure RL and add RL to circuit. Measure VL.3. Calculate IL = VL / RL.4. Calculate Rout = (Voc – VL) / IL.
Schematic
100 KHz square wave with 10 ns rise/fall-time
J 1
J 2 N 4 3 9 3
0
V 1
1 6 . 5
R 16 . 5 k
M 1
M b re a k p
0
V 2TD = 0
TF = 1 0 nP W = 4 . 9 9 uP E R = 1 0 u
V 1 = 1 . 2
TR = 1 0 n
V 2 = 2 . 2
0
V 3
2 . 0
J 2
J 2 N 4 3 9 3
R 26 . 5 k
M 2
M b re a k p
0
0
V 5
2 . 0
V 6
1 . 7
R 31 0
I
V V
I
Time
9.90us 9.95us 10.00us 10.05us 10.10us 10.15us 10.20us 10.25us 10.30us 10.35us 10.40us 10.45us 10.50us 10.55us 10.60us 10.65us 10.70us 10.75us 10.80us 10.85us 10.90us 10.95usV(M1:s)
5.6V
6.0V
6.4V
6.8V
SEL>>
(10.588u,6.63591194)(10.214u,6.63233376)(10.112u,6.64095783)
(9.923u,5.70718765)
V(M2:s)6.1452V
6.1454V
6.1456V
6.1458V
6.1460V
(9.923u,6.14546347)
(10.588u,6.14546299)(10.214u,6.14546776)
(10.06u,6.14536047)
(10.01u,6.14591694)
Voltage Measurements
Aggressor
Victims
Efficiency of Source Follower:Duration of crosstalk to within 25 µVPP: (10.11 – 10.0) = 0.11 µsAfter 0.11 µs, VPP = 4.29 µV.fmax > 2 MHz (assuming 25 µVPP takes 0.5 µs).
Time
9.90us 9.95us 10.00us 10.05us 10.10us 10.15us 10.20us 10.25us 10.30us 10.35us 10.40us 10.45us 10.50us 10.55us 10.60us 10.65us 10.70us 10.75us 10.80us 10.85us 10.90us 10.95usI(R1)
-196.76uA
-196.74uA
-196.72uA
-196.70uA
-196.68uA
SEL>>
(10.207u,-196.6924977u)
(9.949u,-196.7473945u)
I(R2)-196.7214639uA
-196.7214599uA
-196.7214559uA
-196.7214519uA
-196.7214480uA
(10.112u,-196.7214485u)
(10.023u,-196.7214630u)
(9.958u,-196.7214485u)
Current Measurements
Aggressor
Victims
IPP = 54.9 nA
IPP = 14.5 pAt = 10.11 µs – 10.01 µs = 100 ns
Schematic with Bypass Capacitors
J 1
J 2 N 4 3 9 3
0
V 1
1 6 . 5
R 16 . 5 k
M 1
M b re a k p
0
V 2TD = 0
TF = 1 0 nP W = 4 . 9 9 uP E R = 1 0 u
V 1 = 1 . 2
TR = 1 0 n
V 2 = 2 . 2
0
V 3
2 . 0
J 2
J 2 N 4 3 9 3
R 26 . 5 k
M 2
M b re a k p
0
0
V 5
2 . 0
V 6
1 . 7
R 31 0C 1
0 . 1 u
0
C 20 . 1 u
0
I
V V
I
Voltage Measurementswith Bypass Capacitors
Time
9.90us 9.95us 10.00us 10.05us 10.10us 10.15us 10.20us 10.25us 10.30us 10.35us 10.40us 10.45us 10.50us 10.55us 10.60us 10.65us 10.70us 10.75us 10.80us 10.85us 10.90us 10.95usV(M1:s)
5.5V
6.0V
6.5V
7.0V
SEL>>
(10.111u,6.64012461)
(9.942u,5.70718765)
V(M2:s)6.145463V
6.145464V
6.145465V
6.145466V
6.145467V
(10.200u,6.14546347)
(10.022u,6.14546633)
(9.963u,6.14546347)
Aggressor
Victims
Duration of crosstalk to within 25 µVPP: 0.0 nsfmax limited by rise/fall times
VPP = 2.86 µV
Crosstalk Conclusions
1. The voltage supply output resistance should be as small as possible to reduce voltage droops
a. If Rout = 0 Ω: no crosstalk
b. If Rout = 10 Ω: crosstalk is as previously shown
c. Measured Rout ≈ 0.1 Ω
1) Crosstalk will be much less than what was previously shown
2. Adding small (0.1 µF) bypass capacitors to each current source significantly reduces crosstalk to the point of insignificance
Current Source Board (CSB) schematic, layout and mounting
Critical Design Delta Review 2
18
CSB schematic
19
CSB layout
20
potentiometer
SMT JFETThrough Hole JFET 0 ohm resistor
SMT resistor
General procedure for measurement of calibration of a single current source
1. Remove 0 Ω resistor from CSB
2. Ensure potentiometer is at maximum value
3. Connect ammeter using vias on CSB
4. Run System so that current source is active
5. Adjust potentiometer until 200 µA is measured on ammeter
6. Turn off system
7. Reinstall 0 Ω resistor
21
CSB Mounting Side View
23
ARC46 board in adjacent slot
Capacitor on bottom : 4.5 mm
5/8” 4-40 screws
Mating DB connector MOD BRACKET
ARC46 board PCB
DB connector
Current Source Board
1/8” Spacer
Potentiometer : 5 mm
16.5 V Supply
Through Hole Resistor: 1.5 mm
Current Source Board wire
connection to PCB
CSB Mounting Top View
25
5/8” 4-40 screws
Mating DB connectors
MOD BRACKETS
ARC46 board PCB
DB connectors
Current Source Board
Potentiometers
16.5 V Supply
pInput through hole locations on the ARC-46 (not on CSB)
Mounting Holes
Mod Bracket Specifications
26
Top View
Front View Right Side View
4-40 tapped screw hole
4-40 clearance
1.673”
0.250”
0.303”
0.531”
0.750”
0.236”
0.0625”
0.0625” 0.100”
Recommended