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8/11/2019 Introduction to ADCs, Tutorial
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The World Leader in High-Performance Signal Processing SolutionsThe World Leader in High-Performance Signal Processing Solutions
Introduction to A/D Converters
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A/D Converter (ADC) Introduction
A/D Fundamentals
Sampling
Quantization
Factors Affecting A/D Converter Performance
Static Performance
Dynamic Performance
ADC Architectures
SAR ADCs
Pipelined ADCs
Flash Type ADC
Sigma-Delta ADCs
High Speed ADC Application Considerations
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The Measurement & Control Loop
MUXANALOG
SIGNAL
PROCESSOR
A - D
CONVERTER
D - ACONVERTER
ANALOG
SIGNAL
PROCESSOR
MUX
MICRO
PROCESSOR
OR
DSP
PROCESSOR
REFERENCE
Multiplier/Divider
Log Amplifier
rms-dc Converter
F-V/V-F Converter
Operational Amp
Differential Amp
Instrumentation Amp
Isolation Amp
n
bits
n
bits
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ADC SAMPLED ANDQUANTIZED WAVEFORM
DAC RECONSTRUCTEDWAVEFORM
ADC
DAC
DSP MemoryChannel
Analog Digital
timetime
Analog
Digital
Amplitude
Value
REAL WORLD SAMPLED DATA SYSTEMSCONSIST OF ADCs and DACs
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ANALOG
INPUT
DIGITAL
OUTPUTRESOLUTION
N BITS
REFERENCEINPUT
Analog InputDIGITAL OUTPUT CODE = x (2N- 1)
Reference Input
What is an Analog-Digital Converter?
Produces a Digital Output Corresponding to the Value of the SignalApplied to Its Input Relative to a Reference Voltage
Finite Number of Discrete Values : 2N Resulting in QuantizationUncertainty
Changes Continuous Time Signal into Discrete Time SampledRepresentation
Sampling and Quantization Impose Fundamental yet PredictableLimitations
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Sampling Process
Representing a continuous time domain signal at discrete anduniform time intervals
Determines maximum bandwidth of sampled (ADC) or
reconstructed (DAC) signal (Nyquist Criteria)
Frequency Domain- Aliasing for an ADC and Images for a DAC
DISCRETE
TIME SAMPLING
AMPLITUDEQUANTIZATION
y(t)
y(n)
y(n+1)
n-1 n n+1 n+3 ts
t
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Quantization Process
Quantization Process Representing an analog signal having infinite resolution with a digital
word having finite resolution
Determines Maximum Achievable Dynamic Range
Results in Quantization Error/Noise
100
11
10
01
00
Dig
ital
Analog
0 1/4 1/2 3/4 1 = FS
1LSB
Any Analog Input in this
Range Gives the Same
Digital Output Code
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DIGITALO
UTPUT
1 LSB
ANALOG INPUT
1/8 2/8 3/8 4/8 5/8 6/8 7/8
001
010
011
100101
110
111
Conversion Relationshipfor an Ideal A/D Converter
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Quantization Noise
001
010
011
100
101
110
111
1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS
NORMALIZED ANALOG INPUT
DIGITALOUTPUT
quantization noise error
q = 1 LSB
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0 volts
+q/2
-q/2
Quantization Noise (cont)
The RMS value of the quantization noise sawtooth is its peak value,q2, divided by
3, or q
12
For Sine Wave Full Scale RMS Value is 2(N-1)/
2 For Saw Tooth Quantization Error Signal RMS Value is q /12
Thus S/N is 1.225 x 2N
Expressed in dB as 1.76 + 6.02N, where N is the resolution of theA/D converter
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OUTPUT
FSIGNAL FS/2 FS
RMS
QUANTIZATION NOISE
HARMONICS OF FSIGNAL
(EXAGGERATED FOR CLARITY)
If the quantization noise is uncorrelated with the frequency of the
AC input signal, the noise will be spread evenly over the Nyquist
bandwidth of Fs/2.
If, however the input signal is locked to a sub-multiple of the
sampling frequency, the quantization noise will no longer appear
uniform, but as harmonics of the fundamental frequency
Quantization Noise (cont)
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ADC Resolution vs. Quantization Parameters
Resolution,
Bits (n) 2n
LSB, mV
(2.5V FS)
%
Full Scale
ppm
Full Scale
dB
Full Scale
8 256 9.77 0.391 3906 -48.0
10 1024 2.44 0.098 977 -60.0
12 4096 0.610 0.024 244 -72.0
14 16,384 0.153 0.006 61 -84.0
16 65,536 0.038 0.0015 15 -96.0
18 262,164 0.0095 0.00038 3.8 -108.0
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Analog Input Signal Definitions
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Unipolar and Bipolar Converter Codes
0 0 0
FS - 1LSB FS - 1LSB FS - 1LSB
ALL"1"s
1 AND ALL "0"S
ALL"1"s
UNIPOLAR OFFSET BINARY 2s COMPLEMENT
-FS -(FS - 1LSB)
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Factors Affecting A/D Converter Performance- Offset And Gain for Unipolar Ranges
ACTUAL
OFFSET
ERROR
WITH GAIN ERROR:OFFSET ERROR = 0
ACTUAL
IDEAL IDEAL
ZERO ERROR
NO GAIN ERROR:ZERO ERROR = OFFSET ERROR
0 0
GAIN
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ACTUAL
OFFSETERROR
WITH GAIN ERROR:OFFSET ERROR = 0ZERO ERROR RESULTSFROM GAIN ERROR
ACTUAL
IDEAL IDEAL
ZERO ERROR ZERO ERROR
NO GAIN ERROR:ZERO ERROR = OFFSET ERROR
0 0
Factors Affecting A/D Converter Performance- Offset And Gain for Bipolar Ranges
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DC Specifications (Ideal)
Ideal ADC code transitions
are exactly 1 LSBapart.
For an N-bit ADC, there are
2Ncodes. (1 LSB= FS/ 2N )
For this 3-bit ADC, 1 LSB=(1V/23= 1/8th)
Each step is centered on
an eighth of full scale
001
111
110
101
100
011
010
000
1/8 7/83/45/81/23/81/40
Analog Input
DigitalOutput
1 LSB
ADC Transfer Function
(Ideal)
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DC Specifications (DNL)
Differential Non-Linearity
(DNL) is the deviation of an
actual code width from the
ideal 1 LSB code width
Results in narrow or widercode widths than ideal and
can result in missing codes
Results in additive
noise/spurs beyond the
effects of quantization 001
111
110
101
100
011
010
000
1/8 7/83/45/81/23/81/40
Analog Input
DigitalOutput
ADC Transfer Function
(DNL Error)
+1/2 LSB
+1/2 LSB
-1/2 LSB
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DC Specifications (DNL)
DNL error is measured in
lsbs.
A given ADC will have a
typical DNL pattern.
These patterns will alsohave an element of
randomness to them.
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DC Specifications (INL)
Integral Non-Linearity (INL) is
the deviation of an actual code
transition point from its ideal
position on a straight line
drawn between the end points
of the transfer function.
INL is calculated after offset
and gain errors are removed
Results in additive harmonics
and spurs 001
111
110
101
100
011
010
000
1/8 7/83/45/81/23/81/40
Analog Input
DigitalOutput
ADC Transfer Function
(INL Error)
+1/2 LSB
+1 LSB
+1/2 LSB
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DC Specifications (INL)
Some typical INL patterns
Bow indicates 2nd order
nonlinearity
S indicates 3rd order
nonlinearity
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QUANTIFYING ADC DYNAMIC (AC)PERFORMANCE
Harmonic Distortion
Worst Harmonic
Total Harmonic Distortion (THD)
Total Harmonic Distortion Plus Noise (THD + N)
Signal-to-Noise-and-Distortion Ratio (SINAD, or S/N +D) Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Analog Bandwidth (Full-Power, Small-Signal)
Spurious Free Dynamic Range (SFDR)
Two-Tone Intermodulation Distortion
Noise Power Ratio (NPR) or Multitone Power Ratio (MPR)
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Dynamic Testing of A/D Converters
LOW PHASE
JITTER
SINEWAVE SOURCE
A/D CONVERTER
ON
EVALUATION BOARD
BANDPASSFILTER
LOW PHASE
JITTER
SAMPLING
CLOCK SOURCE
FFTANALYZER
POWER
SUPPLIES
A Fast Fou r ier Transform (FFT) Analyzer is used to measure dynamic
performance
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time
amplitud
e
f1
3f1
2f1
frequency
amplitude
f1 2f1 3f1
...to this
Fast Fourier Transform converts
this
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An M-Point FFT
The Effective Noise Floor of an M-Point FFT Is Less Than The RMS Value
of the Quantization Noise
SNR = 6.02N + 1.76 dB
RMS Quantization Noise Level
FFT Floor = 10 log 10(M
2)
0 dB
18 dB, M = 128
21 dB, M = 256
24 dB, M = 512
27 dB, M = 1024
30 dB, M = 2048
33 dB, M = 4096
Bin Spacing = F = FSM
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Actual FFT Plot for AD7484, 14-Bit SARADC Sampling at 3MHz
-140
-120
-100
-80
-60
-40
-20
0
0 200 400 600 800 1000 1200 1400
Frequency (kHz)
dB
fIN= 1.013MHz
SNR = 77.7dB
SNR+D = 77.6dB
THD = -95.5dB
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2 Signals that are Mixed Together Produce Sum and Difference
Frequency Components
Nyquist Theory Stipulates that the Signal Frequency, FSIGNAL must
be < to FSAMPLING to Prevent a Condition Known As Aliasing, in
which the Difference Component Appears Within the Signal
Bandwidth of Interest
Nyquist Bandwidth & Aliasing
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The Signal Frequency Is < 1/2 the Sampling Frequency and So the Sum
and Difference Components Fall Outside (Beyond) the Signal Passband
1 MHz 4 MHz
fsampling fsampling + fsignalfsampling - fsignal
signal
passband
3 MHz 5 MHz
fsignal
The Nyquist Bandwidth & Aliasing(FSIGNAL< FSAMPLING)
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The Signal Frequency Is > 1/2 (approx 2/3) the Sampling Frequency. An
Aliasor False Image is Thus Created that Falls Within the Passband of
Interest.
The Nyquist Bandwidth & Aliasing(FSIGNAL> FSAMPLING)
fsampling- fsignal fsignal fsampling fsampling + fsignal
2.5 MHz1.5 MHz1 MHzAlias
0.5 MHz
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SINAD (Signal-to-Noise-and-Distortion Ratio)
The ratio of the rms signal amplitude to the
mean value of the root-sum-squares (RSS) of all
other spectral components, including
harmonics, but excluding dc
ENOB (Effective Number of Bits)
SNR (Signal-to-Noise Ratio, or Signal-to-Noise
Ratio Without Harmonics) The ratio of the rms signal amplitude to the
mean value of the root-sum-squares (RSS) of all
other spectral components, excluding the first
five harmonics and dc
SINAD, ENOB, and SNR
02.6
76.1 dBSINADENOB
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ADC LARGE SIGNAL (OR FULL POWER)BANDWIDTH
Full-power bandwidth is defined as the input frequencywhere the fundamental in an FFT of the output, rolls offto its 3 dB point
ADCs SHA generally determines the FPBW
FPBW often limited by slew rate of the internal circuitry.
May not be compatible with the converters maximum
operating rate
Ideally fFPBW >> fs/ 2
Many High Speed Converters have fFPBW < fs/ 2
Use as a prerequisite specification for comparing ADCs IF
undersampling capabilities. But need to consider distortionas well.
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Successive Approximation ADC
Recursive One-Bit Sub-Ranging Architecture
ANALOGINPUT
STARTCONVERT
COMPARATOREOC ORDRDY
SHA +
-
DAC
SAR*
*SUCCESSIVEAPPROXIMATION
REGISTER
DIGITALOUTPUT
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Successive Approximation ADC
+FS
-FS
Analog
Input
Period 1
MSB
Bit 4
Bit 3
Bit 2
Period 3Period 2Period 1Period 4Period 3Period 2
AnalogInput
Internal signals for a 4-bit successive approximation ADC
test at 1
test at 1
test at 1
test at 1
test at 1
test at 1
test at 10
00
0
0
0
0
00
0
0
01
0
1
0
11
1
00
Conversion complete (1011),
start on next conversion
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How a Successive Approximation A/DConverter Works
Rising/Falling Edge of Convert Start Pulse Resets Logic
Falling/Rising Edge Begins Conversion Process
Bit Comparisons Made on Each Clock Edge
Conversion Time Equals Number of Comparisons
(Resolution) Times Clock Period
The Accuracy of Conversion Depends on the DAC Linearity
and Comparator Noise
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EXAMPLE : ANALOG INPUT = 6.428V, REFERENCE = 10.000V
MSB
5.000V2SB
2.500V
3SB
1.250V
LSB
0.625V
VIN> 5.000V VIN> 6.875VVIN> 6.250VVIN> 7.500V
YES
1
NO
0
YES
1
NO
0
How Successive Approximation Works
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Advantages to SAR A/D converters
Low Power (12-bit/1.5 MSPS ADC: 1.7 mW)
Higher resolutions (16-bit/1 MSPS)
Small Die Area and Low Cost
No pipeline delay
Tradeoffs to SAR A/D converters
Lower sampling rates
Typical Applications
Instrumentation
Industrial control
Data acquisition
Successive Approximation ADC
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Pipelined Sub-ranging ADC
Conversion divided intodiscrete stages thuscausing pipeline delay
1st Stage ADC is 6-bit
FLASH 2nd Stage ADC is 7-bit
Flash
Total resolution is 12bits (one bit used for
error correction)
ANALOG
INPUT
7
12
SHA
1
6-BIT
ADC
7-BIT
ADC
GAIN
6
+
-
ERROR CORRECTION LOGIC
6-BIT
DAC
SHA
2
SHA
3
OUTPUT REGISTER
12
BUFFER
REGISTER
6
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Pipelined Sub-ranging ADC
Advantages to Pipelined Sub-ranging A/D
convertersHigher resolutions at high-speeds (14-bits/105 MSPS)
Digitize wideband inputs
Tradeoffs to pipelined sub-ranging A/Dconverters
Higher power dissipation
Larger die size
Typical Applications
Communications
Medical imaging
Radar
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OVERSAMPLING, DIGITAL FILTERING,NOISE SHAPING, AND DECIMATION
fs
2
fs
QUANTIZATIONNOISE = q / 12
q = 1 LSBADC
fs NyquistOperation
A
KfsKfs
2
fs
2
REMOVED NOISES
MOD
DIGITAL
FILTER
Kfs
DEC
fs
Oversampling
+ Noise Shaping
+ Digital Filter+ DecimationC
Kfs
2
Kfsfs
2
DIGITAL FILTER
REMOVED NOISEADCDIGITAL
FILTER
Kfs
Oversampling
+ Digital Filter
+ DecimationB
DEC
fs
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DEFINITION OF "NOISE-FREE"CODE RESOLUTION
EFFECTIVE
RESOLUTION= log2
FULLSCALE RANGE
RMS NOISE BITS
P-P NOISE = 6.6 RMS NOISE
NOISE-FREE
CODE RESOLUTION= log2
FULLSCALE RANGE
P-P NOISEBITS
= EFFECTIVE RESOLUTION 2.72 BITS
NOISE-FREE
CODE RESOLUTION= log2
FULLSCALE RANGE
6.6 RMS NOISEBITS
0.4uVrms
20mV
16.5bits
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High Speed ADC Time DomainSpecifications Considerations
Aperture Jitter and Delay
ADC Pipeline Delay
Duty Cycle Sensitivity
DNL Effects
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SNR DUE TO APERTURE AND SAMPLINGCLOCK JITTER
SNR
(dB)
ENOB
FULLSCALESINEWAVE INPUT FREQUENCY(MHz)
100
80
60
40
20
0
16
14
12
10
8
6
4
1 3 10 30 100
SNR = 20log10
1
2ftj
tj=1ps
tj=10ps
tj=100ps
tj=1ns
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ANALOGINPUT
SAMPLINGCLOCK
OUTPUTDATA
DATA N - 3 DATA N - 2 DATA N - 1 DATA N
N N + 1 N + 2 N + 3
Many High Speed ADCs, such as subranging types, usepipeline architectures to:
Reduce chip size, and power consumption
Allows multiple samples to be converted simultaneously in ADC
Results in fixed delay between Sampled Input and corresponding
digital output.
ADC LATENCY OR PIPELINE DELAY
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ADC DUTY CYCLE SENSITIVITY
High Speed ADCs are oftensensitive to duty cycle of theCLK input
CLK oscillators are usuallyspecified as 40/60 or 45/55
Digital Specifications ofdatasheet provide aminimum CLK HIGH/LOWperiod (nsec) to achieverated performance.
Some datasheets show
SNR/THD graphs as afunction of duty cycle
Note, ADC also has minimumspecified sample rate
TPC 15. SINAD/SFDR vs. Duty Cycle @ FIN=20 MHz
45
50
55
60
65
70
75
80
85
90
30 35 40 45 50 55 60 65 70
%Positive Duty Cycle
dBc
SINAD-Clock Stabilizer ON
SINAD-Clock Stabilizer OFF
SFDR-Clock Stabilizer ON
SFDR-Clock Stabilizer OFF
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Example : AD9433 SFDR
SFDR ENABLED
DISABLED
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Example : AD9433 SFDR
SFDR
ENABLED
DISABLED
Encode = 105Msps
Ain = 70MHz, -0.5dBFs
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Example of Data Sheet Specifications forAD7476 ADC
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For complete information
on the Worlds most extensive line of
A/D converters visit
WWW.ANALOG.COM
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